/linux-master/drivers/net/pcs/ |
H A D | pcs-xpcs-nxp.c | 74 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL2, 89 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0, 94 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1, 100 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER1_0, 107 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_0, val); 113 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_1, val); 122 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_TRIM, val); 127 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DATAPATH_1, 0); 134 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0, 139 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL [all...] |
H A D | pcs-xpcs.c | 292 dev = MDIO_MMD_VEND2; 395 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); 402 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); 648 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0); 665 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret); 669 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1); 678 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret); 706 mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); 711 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, 717 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTR [all...] |
H A D | pcs-lynx.c | 45 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); 54 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); 165 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE,
|
/linux-master/drivers/net/phy/ |
H A D | dp83td510.c | 13 /* MDIO_MMD_VEND2 registers */ 61 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 67 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 73 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 78 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 93 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1); 140 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 183 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT);
|
H A D | microchip_t1s.c | 93 * 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2 99 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, 104 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, 109 return phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_DATA); 138 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 153 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 204 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 223 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); 229 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_STS2); 245 err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, [all...] |
H A D | intel-xway.c | 255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, 259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, 272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); 273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); 274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); 275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); 276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); 277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);
|
H A D | dp83tg720.c | 12 /* MDIO_MMD_VEND2 registers */ 97 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_SQI_REG_1); 135 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
|
H A D | marvell10g.c | 195 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 272 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 279 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 326 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 335 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 349 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 665 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); 677 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 683 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 1336 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTR [all...] |
H A D | phy-c45.c | 1290 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); 1299 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); 1305 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); 1312 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); 1318 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); 1351 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1366 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1383 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1391 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1406 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, [all...] |
H A D | adin1100.c | 148 int rc = phy_read_mmd(phydev, MDIO_MMD_VEND2, 168 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, 177 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND2,
|
H A D | marvell-88x2222.c | 78 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, 83 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST, 199 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, 202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, 205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
|
H A D | ncn26000.c | 45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR,
|
H A D | mediatek-ge-soc.c | 212 /* Registers on MDIO_MMD_VEND2 */ 364 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, 1148 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1171 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 1247 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1253 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, 1353 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1364 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? 1392 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
|
H A D | mxl-gpy.c | 689 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 696 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 703 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 716 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 730 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 766 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL);
|
H A D | nxp-c45-tja11xx-macsec.c | 301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); 307 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); 321 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); 327 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr);
|
H A D | phy_device.c | 808 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { 850 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
|
/linux-master/drivers/net/ethernet/microchip/ |
H A D | lan743x_ethtool.c | 1240 { ETH_SR_MII_CTRL, MDIO_MMD_VEND2, 0x0000}, 1241 { ETH_SR_MII_STS, MDIO_MMD_VEND2, 0x0001}, 1242 { ETH_SR_MII_DEV_ID1, MDIO_MMD_VEND2, 0x0002}, 1243 { ETH_SR_MII_DEV_ID2, MDIO_MMD_VEND2, 0x0003}, 1244 { ETH_SR_MII_AN_ADV, MDIO_MMD_VEND2, 0x0004}, 1245 { ETH_SR_MII_LP_BABL, MDIO_MMD_VEND2, 0x0005}, 1246 { ETH_SR_MII_EXPN, MDIO_MMD_VEND2, 0x0006}, 1247 { ETH_SR_MII_EXT_STS, MDIO_MMD_VEND2, 0x000F}, 1248 { ETH_SR_MII_TIME_SYNC_ABL, MDIO_MMD_VEND2, 0x0708}, 1249 { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR, MDIO_MMD_VEND2, [all...] |
H A D | lan743x_main.c | 1003 mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, 1019 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, 1024 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, 1029 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, 1049 ret = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, 1081 mii_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR); 1085 an_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, VR_MII_AN_CTRL); 1089 dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, 1105 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, 1116 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMC [all...] |
/linux-master/drivers/net/ethernet/amd/xgbe/ |
H A D | xgbe-mdio.c | 151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); 153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); 160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); 179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); 368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); 377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); 663 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); 670 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STA [all...] |
H A D | xgbe-phy-v2.c | 1659 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1660 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
|
/linux-master/drivers/net/dsa/sja1105/ |
H A D | sja1105_mdio.c | 20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) 23 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) 25 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) 46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) 67 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) 69 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2)
|
H A D | sja1105_main.c | 2318 MDIO_MMD_VEND2, MDIO_CTRL1);
|
/linux-master/include/uapi/linux/ |
H A D | mdio.h | 28 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ macro 159 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
|
/linux-master/drivers/net/dsa/ |
H A D | mt7530.c | 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 2683 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2686 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
|