/linux-master/drivers/net/phy/ |
H A D | marvell-88q2xxx.c | 103 { MDIO_MMD_PCS, 0x8033, 0x6801 }, 107 { MDIO_MMD_PCS, 0xfe1b, 0x48 }, 108 { MDIO_MMD_PCS, 0xffe4, 0x6b6 }, 110 { MDIO_MMD_PCS, MDIO_CTRL1, 0x0 }, 114 { MDIO_MMD_PCS, 0xfe79, 0x0 }, 115 { MDIO_MMD_PCS, 0xfe07, 0x125a }, 116 { MDIO_MMD_PCS, 0xfe09, 0x1288 }, 117 { MDIO_MMD_PCS, 0xfe08, 0x2588 }, 118 { MDIO_MMD_PCS, 0xfe11, 0x1105 }, 119 { MDIO_MMD_PCS, [all...] |
H A D | bcm87xx.c | 114 pcs_status = phy_read_mmd(phydev, MDIO_MMD_PCS, 144 reg = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_CONTROL); 150 err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS); 155 err = phy_write_mmd(phydev, MDIO_MMD_PCS, 159 err = phy_write_mmd(phydev, MDIO_MMD_PCS, 164 err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS);
|
H A D | marvell-88x2222.c | 90 int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, 100 int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, 119 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 130 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 140 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 292 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_ADVERTISE, 307 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); 315 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT); 328 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); 364 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STA [all...] |
H A D | smsc.c | 280 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, 286 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_MCFGR, 304 rc = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR); 376 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, 382 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, 390 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, *mask); 400 phy_write_mmd(phydev, MDIO_MMD_PCS, reg, 0); 424 rc = phy_read_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR); 486 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, 493 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCS [all...] |
H A D | marvell10g.c | 200 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 357 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 362 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 376 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1); 399 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, 418 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2, 428 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, 437 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 478 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 924 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR [all...] |
H A D | adin1100.c | 221 return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, 225 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL,
|
H A D | microchip.c | 325 val = phy_read_mmd(phydev, MDIO_MMD_PCS, 329 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
|
/linux-master/drivers/net/ethernet/amd/xgbe/ |
H A D | xgbe-phy-v1.c | 322 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 325 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 330 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 373 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); 376 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); 378 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 381 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); 416 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); 419 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); 421 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL [all...] |
H A D | xgbe-mdio.c | 164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); 166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); 173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); 175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); 1557 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1)); 1559 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1)); 1561 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1)); 1563 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2)); 1565 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1)); 1567 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS [all...] |
H A D | xgbe-pci.c | 446 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 448 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); 462 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
|
H A D | xgbe-platform.c | 498 pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); 500 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); 516 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
|
/linux-master/drivers/net/phy/qcom/ |
H A D | qca808x.c | 117 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 119 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 121 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 123 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 125 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 127 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 212 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 218 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 348 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 349 phy_write_mmd(phydev, MDIO_MMD_PCS, [all...] |
H A D | qca83xx.c | 60 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 116 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
|
H A D | qcom-phy-lib.c | 83 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 536 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 598 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
|
H A D | at803x.c | 371 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 386 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 391 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 837 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 878 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 883 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
|
H A D | qca807x.c | 633 MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL); 636 MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL, val);
|
/linux-master/drivers/vfio/platform/reset/ |
H A D | vfio_platform_amdxgbe.c | 69 pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1); 71 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1, pcs_value); 76 pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS,
|
/linux-master/drivers/net/ethernet/chelsio/cxgb/ |
H A D | mv88x201x.c | 46 cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8304, 0xdddd); 214 cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val); 215 cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val | 1); 219 cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val);
|
/linux-master/drivers/net/pcs/ |
H A D | pcs-xpcs-wx.c | 163 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL2); 196 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBR); 202 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBX); 204 xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL1, 0);
|
H A D | pcs-xpcs.c | 232 return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); 237 return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); 287 dev = MDIO_MMD_PCS; 322 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); 331 ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); 340 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); 347 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); 929 pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); 1238 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); 1244 ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID [all...] |
/linux-master/drivers/net/ethernet/sfc/falcon/ |
H A D | txc43128_phy.c | 212 ctrl = ef4_mdio_read(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL); 214 ef4_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl); 265 ef4_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl); 272 return txc_bist_one(efx, MDIO_MMD_PCS, TXC_BIST_CTRL_TYPE_TSD); 403 txc_glrgs_lane_power(efx, MDIO_MMD_PCS); 436 txc_reset_logic_mmd(efx, MDIO_MMD_PCS);
|
H A D | qt202x_phy.c | 81 reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG); 112 reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG); 167 firmware_id[i] = ef4_mdio_read(efx, MDIO_MMD_PCS, 464 mmd = MDIO_MMD_PCS;
|
H A D | tenxpress.c | 151 ef4_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
|
H A D | mdio_10g.c | 190 ef4_mdio_set_flag(efx, MDIO_MMD_PCS,
|
/linux-master/include/uapi/linux/ |
H A D | mdio.h | 21 #define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */ macro 152 #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
|