Searched refs:MASK (Results 1 - 25 of 107) sorted by relevance

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/linux-master/drivers/iommu/intel/
H A Dcap_audit.h67 #define DO_CHECK_FEATURE_MISMATCH(a, b, cap, feature, MASK) \
70 intel_iommu_##cap##_sanity &= ~(MASK); \
75 #define CHECK_FEATURE_MISMATCH(a, b, cap, feature, MASK) \
76 DO_CHECK_FEATURE_MISMATCH((a)->cap, (b)->cap, cap, feature, MASK)
78 #define CHECK_FEATURE_MISMATCH_HOTPLUG(b, cap, feature, MASK) \
82 (b)->cap, cap, feature, MASK); \
85 #define MINIMAL_FEATURE_IOMMU(iommu, cap, MASK) \
87 u64 min_feature = intel_iommu_##cap##_sanity & (MASK); \
88 min_feature = min_t(u64, min_feature, (iommu)->cap & (MASK)); \
89 intel_iommu_##cap##_sanity = (intel_iommu_##cap##_sanity & ~(MASK)) | \
[all...]
/linux-master/include/linux/soc/ti/
H A Dknav_dma.h17 #define MASK(x) (BIT(x) - 1) macro
18 #define KNAV_DMA_DESC_PKT_LEN_MASK MASK(22)
22 #define KNAV_DMA_DESC_TAG_MASK MASK(8)
30 #define KNAV_DMA_DESC_PSLEN_MASK MASK(6)
32 #define KNAV_DMA_DESC_ERR_FLAG_MASK MASK(4)
34 #define KNAV_DMA_DESC_PSFLAG_MASK MASK(4)
36 #define KNAV_DMA_DESC_RETQ_MASK MASK(14)
37 #define KNAV_DMA_DESC_BUF_LEN_MASK MASK(22)
38 #define KNAV_DMA_DESC_EFLAGS_MASK MASK(4)
/linux-master/tools/testing/selftests/ftrace/test.d/ftrace/
H A Dfunc_cpumask.tc29 MASK=0x`cat tracing_cpumask`
30 test `printf "%d" $MASK` -eq 2 || do_reset
/linux-master/tools/testing/selftests/bpf/progs/
H A Dtest_pkt_md_access.c11 #define TEST_FIELD(TYPE, FIELD, MASK) \
14 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
19 #define TEST_FIELD(TYPE, FIELD, MASK) \
23 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk20a.h30 #define MASK(w) ((1 << (w)) - 1) macro
49 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)
59 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)
87 #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
92 #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
94 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\
95 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))
H A Dgm20b.c41 (MASK(GPCPLL_CFG2_SDM_DIN_WIDTH) << GPCPLL_CFG2_SDM_DIN_SHIFT)
45 (MASK(GPCPLL_CFG2_SDM_DIN_NEW_WIDTH) << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT)
53 (MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH) << GPCPLL_DVFS0_DFS_COEFF_SHIFT)
57 (MASK(GPCPLL_DVFS0_DFS_DET_MAX_WIDTH) << GPCPLL_DVFS0_DFS_DET_MAX_SHIFT)
169 MASK(GPCPLL_CFG2_SDM_DIN_WIDTH);
201 dvfs->dfs_coeff = min_t(u32, coeff, MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH));
254 rem = ((u32)n) & MASK(DFS_DET_RANGE);
259 *sdm_din = (rem >> BITS_PER_BYTE) & MASK(GPCPLL_CFG2_SDM_DIN_WIDTH);
536 nvkm_mask(device, GPC_BCAST_GPCPLL_DVFS2, MASK(DFS_DET_RANGE + 1),
788 data &= MASK(GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDT
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask);
54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask);
152 REG_UPDATE(MASK_reg, MASK, 1);
158 REG_UPDATE(MASK_reg, MASK, 1);
164 REG_UPDATE(MASK_reg, MASK, 1);
168 REG_UPDATE(MASK_reg, MASK, 0);
172 REG_UPDATE(MASK_reg, MASK, 0);
H A Dgeneric_regs.h38 GENERIC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
H A Dddc_regs.h41 DDC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
64 DDC_GPIO_VGA_REG_LIST_ENTRY(MASK, cd),\
81 DDC_GPIO_I2C_REG_LIST_ENTRY(MASK, cd),\
H A Dhpd_regs.h46 HPD_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
/linux-master/arch/arm/mach-rpc/
H A Dirq.c15 #define MASK 0x08 macro
130 val = readb(base + MASK);
131 writeb(val & ~mask, base + MASK);
140 val = readb(base + MASK);
141 writeb(val & ~mask, base + MASK);
149 val = readb(base + MASK);
150 writeb(val | mask, base + MASK);
/linux-master/sound/soc/codecs/
H A Dak4613.c425 #define MASK(x) (1 << AK4613_CHANNEL_##x) macro
428 [AK4613_CONFIG_MODE_STEREO] = { MASK(2), MASK(2), MASK(2), MASK(2)},
429 [AK4613_CONFIG_MODE_TDM512] = { MASK(4), MASK(12), MASK(12), MASK(12)},
430 [AK4613_CONFIG_MODE_TDM256] = { MASK(
[all...]
/linux-master/arch/x86/kernel/cpu/mce/
H A Dseverity.c66 #define MASK(x, y) .mask = x, .result = y macro
115 SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB)
119 SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB)
130 SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0),
137 SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
142 MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
158 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR),
163 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
168 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
173 SER, MASK(MCI_STATUS_OVE
[all...]
/linux-master/scripts/
H A Dgfp-translate79 MASK=`echo $LINE | awk '{print $3}'`
80 if [ $(($GFPMASK&$MASK)) -ne 0 ]; then
/linux-master/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h13 #define MASK(x) (BIT(x) - 1) macro
17 #define FRM_END_START_MASK MASK(2)
50 #define CH_OVLY_SEL_MASK MASK(2)
99 #define QOSGENERATOR_MODE_MASK MASK(2)
/linux-master/net/openvswitch/
H A Ddatapath.h276 /* 'KEY' must not have any bits set outside of the 'MASK' */
277 #define OVS_MASKED(OLD, KEY, MASK) ((KEY) | ((OLD) & ~(MASK)))
278 #define OVS_SET_MASKED(OLD, KEY, MASK) ((OLD) = OVS_MASKED(OLD, KEY, MASK))
/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Dcursor.c46 MASK(NV_CIO_CRE_HCUR_ASI) |
52 MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
/linux-master/drivers/scsi/sym53c8xx_2/
H A Dsym_fw2.h228 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
316 SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)),
348 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
438 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
462 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
521 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
681 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
898 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
904 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1073 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_I
[all...]
H A Dsym_fw1.h236 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
363 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
453 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
478 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
538 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
704 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
949 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
955 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
1187 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1207 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_I
[all...]
/linux-master/include/linux/irqchip/
H A Darm-gic-v3.h181 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
183 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
208 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
210 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
277 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK)
279 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK)
315 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK)
317 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK)
419 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
421 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
[all...]
/linux-master/arch/x86/crypto/
H A Dpoly1305-x86_64-cryptogams.pl419 my ($H0,$H1,$H2,$H3,$H4, $T0,$T1,$T2,$T3,$T4, $D0,$D1,$D2,$D3,$D4, $MASK) =
888 vmovdqa 64(%rcx),$MASK # .Lmask26
898 vpand $MASK,$T0,$T0 # 0
900 vpand $MASK,$T1,$T1 # 1
902 vpand $MASK,$T2,$T2 # 2
903 vpand $MASK,$T3,$T3 # 3
1052 vpand $MASK,$H0,$H0 # 0
1054 vpand $MASK,$H1,$H1 # 1
1057 vpand $MASK,$H2,$H2 # 2
1058 vpand $MASK,
[all...]
/linux-master/tools/perf/dlfilters/
H A Ddlfilter-show-cycles.c25 #define MASK (TABLESZ - 1) macro
49 __u32 pos = tid & MASK;
/linux-master/arch/arm/crypto/
H A Dghash-ce-core.S59 MASK .req d28
163 vmull.p64 T1, XL_L, MASK
170 vmull.p64 XL, T1_H, MASK
229 vmov.i8 MASK, #0xe1
230 vshl.u64 MASK, MASK, #57
298 vmov.i8 MASK, #0xe1
299 vshl.u64 MASK, MASK, #57
341 vmov.i8 MASK, #
[all...]
/linux-master/include/video/
H A Dgbe.h81 #define MASK(msb, lsb) \ macro
84 ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
86 ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
/linux-master/drivers/scsi/
H A Dvmw_pvscsi.h31 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
410 #define PVSCSI_INTR_CMPL_MASK MASK(2)
414 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
416 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)

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