Searched refs:L2 (Results 1 - 25 of 59) sorted by relevance

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/linux-master/arch/powerpc/boot/dts/fsl/
H A Dmpc8572si-pre.dtsi64 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
H A Dp1020si-pre.dtsi62 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
H A Dp1021si-pre.dtsi62 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
H A Dp1022si-pre.dtsi64 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
H A Dp1023si-pre.dtsi70 next-level-cache = <&L2>;
76 next-level-cache = <&L2>;
H A Dp2020si-pre.dtsi63 next-level-cache = <&L2>;
69 next-level-cache = <&L2>;
H A Dbsc9131si-pre.dtsi59 next-level-cache = <&L2>;
H A Dc293si-pre.dtsi60 next-level-cache = <&L2>;
H A Dmpc8536si-pre.dtsi63 next-level-cache = <&L2>;
H A Dmpc8544si-pre.dtsi63 next-level-cache = <&L2>;
H A Dmpc8548si-pre.dtsi64 next-level-cache = <&L2>;
H A Dmpc8568si-pre.dtsi63 next-level-cache = <&L2>;
H A Dmpc8569si-pre.dtsi62 next-level-cache = <&L2>;
H A Dp1010si-pre.dtsi64 next-level-cache = <&L2>;
/linux-master/arch/arc/kernel/
H A Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
156 ; -L2 interrupts L1 (before L1 ISR could run)
159 ; Returns from L2 context fine
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
165 ; L2 interrupting L1 implies both L2 and L1 active
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
209 ; out of the L2 interrupt context (drop to pure kernel mode) and jump
320 ; use the same priority as rtie: EXCPN, L2 IR
[all...]
/linux-master/security/apparmor/include/
H A Dlabel.h163 #define next_comb(I, L1, L2) \
166 if ((I).j >= (L2)->size) { \
173 /* for each combination of P1 in L1, and P2 in L2 */
174 #define label_for_each_comb(I, L1, L2, P1, P2) \
176 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
177 (I) = next_comb(I, L1, L2))
179 #define fn_for_each_comb(L1, L2, P1, P2, FN) \
183 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
243 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \
247 label_for_each ## __VA_ARGS__(i, (L1), (L2), (
[all...]
H A Dperms.h168 * TODO: optimize the walk, currently does subwalk of L2 for each P in L1
186 #define xcheck_ns_labels(L1, L2, FN, args...) \
189 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
193 #define xcheck_labels_profiles(L1, L2, FN, args...) \
194 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
196 #define xcheck_labels(L1, L2, P, FN1, FN2) \
197 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
/linux-master/arch/sparc/net/
H A Dbpf_jit_64.h22 #define L2 0x12 macro
/linux-master/arch/m68k/lib/
H A Ddivsi3.S103 jpl L2
111 L2: movel d1, sp@- label
/linux-master/arch/arm/mm/
H A Dl2c-l2x0-resume.S4 * the settings of their L2 cache controller before restoring the
35 @ and can be written whether or not the L2 cache is enabled
43 @ Don't setup the L2 cache if it is already enabled
/linux-master/lib/
H A Dtest_dynamic_debug.c92 enum cat_level_names { L0 = 22, L1, L2, L3, L4, L5, L6, L7 }; enumerator in enum:cat_level_names
94 "L0", "L1", "L2", "L3", "L4", "L5", "L6", "L7");
134 prdbg(L2);
/linux-master/drivers/net/ethernet/intel/iavf/
H A Diavf_common.c480 /* L2 Packet types */
482 IAVF_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
483 IAVF_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
484 IAVF_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
487 IAVF_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
488 IAVF_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
491 IAVF_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
492 IAVF_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
493 IAVF_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
494 IAVF_PTT(13, L2, NON
[all...]
/linux-master/arch/sh/lib/
H A D__clear_user.S82 .L2: dt r3
84 bf/s .L2
/linux-master/arch/riscv/lib/
H A Dtishift.S14 blez a5, .L2
23 .L2:
/linux-master/arch/powerpc/perf/
H A Disa207-common.c226 ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
260 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
262 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM);
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0);
271 ret = PH(LVL, L2) | LEVEL(L2) | RE
[all...]

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