Searched refs:IP2_15_12 (Results 1 - 9 of 9) sorted by last modified time

/linux-master/drivers/pinctrl/renesas/
H A Dpfc-r8a7779.c823 PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
824 PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
825 PINMUX_IPSR_GPSR(IP2_15_12, MDATA),
826 PINMUX_IPSR_GPSR(IP2_15_12, TX0_C),
827 PINMUX_IPSR_GPSR(IP2_15_12, SUB_TMS),
828 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE1),
829 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE9),
830 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE17),
831 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE25),
832 PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE3
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H A Dpfc-r8a77980.c50 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
217 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
322 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
553 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
554 PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
555 PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
556 PINMUX_IPSR_GPSR(IP2_15_12, A19),
557 PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
2711 IP2_15_12
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H A Dpfc-r8a77970.c48 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
183 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
272 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
471 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
472 PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
473 PINMUX_IPSR_GPSR(IP2_15_12, A19),
474 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
2257 IP2_15_12
H A Dpfc-r8a77995.c76 #define GPSR1_12 F_(DU_DG4, IP2_15_12)
229 #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
363 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
609 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
610 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
611 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
2698 IP2_15_12
H A Dpfc-r8a77990.c116 #define GPSR2_22 F_(BS_N, IP2_15_12)
233 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
389 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
624 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
625 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
626 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
627 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
628 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
629 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_
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H A Dpfc-r8a77965.c128 #define GPSR1_4 F_(A4, IP2_15_12)
278 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
770 PINMUX_IPSR_GPSR(IP2_15_12, A4),
771 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
772 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
773 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
774 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
775 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB
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H A Dpfc-r8a7796.c128 #define GPSR1_4 F_(A4, IP2_15_12)
278 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
768 PINMUX_IPSR_GPSR(IP2_15_12, A4),
769 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
770 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
771 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
772 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
773 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB
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H A Dpfc-r8a77951.c123 #define GPSR1_4 F_(A4, IP2_15_12)
275 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
448 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
764 PINMUX_IPSR_GPSR(IP2_15_12, A4),
765 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
766 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
767 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
768 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
769 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB
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H A Dpfc-r8a77470.c629 PINMUX_IPSR_GPSR(IP2_15_12, D9),
630 PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
631 PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
632 PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
2740 /* IP2_15_12 [4] */

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