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0256b6ae |
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08-Mar-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Annotate sentinels in tables It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Hence drop all such commas. Add comments to clarify the purpose of the empty elements. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/845f1d8285dd44522af1b0f429d4c6bd4759eb9e.1678272180.git.geert+renesas@glider.be
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d04b961d |
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08-Mar-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: r8a77995: Add support for AVB power-source Add support for configuring the I/O voltage level of the Ethernet AVB pins on the R-Car D3 SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or 3.3V operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8f9164487715d8a4898ca651038c0b4d5013764c.1678271030.git.geert+renesas@glider.be
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a3ca1e18 |
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08-Mar-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flag Commit 537db25ca330dce0 ("pinctrl: renesas: Add I/O voltage level flag") introduced new flags to support pins that can switch their voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V. The old SH_PFC_PIN_CFG_IO_VOLTAGE flag was retained to avoid having to change existing drivers. Replace SH_PFC_PIN_CFG_IO_VOLTAGE by SH_PFC_PIN_CFG_IO_VOLTAGE_18_33, to make the voltage configuration explicit, and to prepare for the advent of support for more voltage levels. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ae5f879c093f3e3cd50ba1495975bccfad81237b.1678271030.git.geert+renesas@glider.be
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31f0a454 |
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08-Mar-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resume The POC Control Register 0 (POCCTRL0) on R-Car D3 is not registered in the pinmux_ioctrl_regs[] array. Hence it is not saved/restored during suspend/resume, and its contents may be lost after s2ram. This went unnoticed when improving suspend/resume support in commit d92ee9cf8ec8d7fe ("pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume"). Fix this by moving the pinmux_ioctrl_regs[] array up, and adding the POCCTRL0 register. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d17402b83b1f3fa0f572527c0382027bccb86205.1678271030.git.geert+renesas@glider.be
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ec255e1c |
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13-Apr-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: r8a77995: Optimize fixed-width reserved fields Describe registers with fixed-width register fields and many reserved fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a shorthand not requiring dummy values. This reduces kernel size by 422 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d74af80fdb7b6d78b10634238a88e55a139e5c22.1649865241.git.geert+renesas@glider.be
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de3561ba |
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13-Apr-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: r8a77995: Use shorthands for reserved fields Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 246 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7098704f89bb702c28036c567d3222521ff60f86.1649865241.git.geert+renesas@glider.be
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ff06501c |
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29-Mar-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: r8a77995: Add QSPI and RPC pins, groups, and functions Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77995 PFC driver. They are to be used when a QSPI Flash, Octal-SPI Flash, or HyperFlash is connected. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/19a3bccd0ec830846578a38b4c80dccb195109a0.1648547080.git.geert+renesas@glider.be
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410ba4ad |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Pass sh_pfc_soc_info to rcar_pin_to_bias_reg() Currently rcar_pin_to_bias_reg() takes a struct sh_pfc pointer, which is only available after the pin control driver has been initialized, thus preventing the checker from calling this function for validating consistency of the pin control tables. Fix this by replacing the parameter by a struct sh_pfc_soc_info pointer. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/3065a12dde606bacec9e5f14f10cabeaae75e265.1640270559.git.geert+renesas@glider.be
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b67fc1c6 |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Remove unused pfc parameter from .pin_to_pocctrl() The pfc parameter of the .pin_to_pocctrl() method was never used. It is a relic of the old I/O voltage handling before commit 8775306dcf48092f ("pinctrl: sh-pfc: refactor voltage setting"). Remove the parameter, as it prevents the checker from calling this function for validating consistency of the pin control tables. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/822133086f32618c7fc920123c6a96f5d4ea7ad6.1640270559.git.geert+renesas@glider.be
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54a13d68 |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: r8a77995: Share MMC pin group data Pin groups mmc_data[14] are subsets of mmc_data8. This reduces kernel size by 40 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8da25ab2d65c31d9300b59d28b80c326aae9e787.1640269757.git.geert+renesas@glider.be
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496da100 |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Add generic support for resizable buses The VIN_DATA_PIN_GROUP() macro and vin_data{12,16,} unions are used to define multiple VIN data groups with different numbers of lanes, while referring to a single array of data pins, thus saving memory. However, the same feature would be useful for other resizable buses, like MMC, SDHI, QSPI, LCD, BSC, ... Rework the mechanism for generic use: - Use the new SH_PFC_PIN_GROUP_SUBSET() helper to remove the need for bus-specific unions, - Rename VIN_DATA_PIN_GROUP() to BUS_DATA_PIN_GROUP(), - Rename the macro parameters to better reflect their purposes, - Move the macro up, where it belongs. Update all individual pin control drivers for the above changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/cccfcfd01eb8ab7a587b084c4ddbf97293bd7291.1640269757.git.geert+renesas@glider.be
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c614d12c |
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23-Dec-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Rename sh_pfc_soc_operations instances Some instances of struct sh_pfc_soc_operations are called "<soc>_pfc_ops", others are called "<soc>_pinmux_ops" or just "pinmux_ops". Settle on the first variant, to avoid confusion with "struct pinmux_ops" in the pinctrl core, and to increase consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2ab33ad1d6a20a57d16922678b78810fa55b7fc0.1640269757.git.geert+renesas@glider.be
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5a2a1c71 |
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26-Jan-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: r8a77995: Restore pin group sort order Move the msiof* pin groups where they belong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/da1018c56134b910121b085b736fe7f664b96df1.1643199959.git.geert+renesas@glider.be
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96310a12 |
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25-Dec-2021 |
Nikita Yushchenko <nikita.yoush@cogentembedded.com> |
pinctrl: renesas: r8a7799[05]: Add MediaLB pins This adds pins, groups, and functions for MediaLB devices on Renesas R-Car E3 and D3 SoCs. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211225191713.2187975-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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e9d66bdb |
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30-Jun-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: r8a77995: Add bias pinconf support Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using some parts from the common R-Car bias handling, which requires making rcar_pin_to_bias_reg() public. R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE# (GP_3_1) pins. Unlike all other pins, they are controlled by different bits in the LSI pin pull-up/down control register (PUD2) than in the LSI pin pull-enable register (PUEN2). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
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4b6e6c19 |
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03-Mar-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Move R-Car bias helpers to sh_pfc.h The Renesas Pin Function Controller driver uses two header files: - sh_pfc.h, for use by both core code and SoC-specific drivers, - core.h, for internal use by the core code only. Hence move the R-Car bias helper declarations from core.h to sh_pfc.h, and drop the inclusion of core.h from SoC-specific drivers that no longer need it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-3-geert+renesas@glider.be
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077365a9 |
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09-Sep-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: Rename sh-pfc to renesas The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
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