Searched refs:GICR_CTLR (Results 1 - 6 of 6) sorted by relevance

/linux-master/tools/testing/selftests/kvm/include/aarch64/
H A Dgic_v3.h42 #define GICR_CTLR 0x000 macro
/linux-master/tools/testing/selftests/kvm/lib/aarch64/
H A Dgic_v3.c48 while (readl(redist_base + GICR_CTLR) & GICR_CTLR_RWP) {
/linux-master/include/linux/irqchip/
H A Darm-gic-v3.h114 #define GICR_CTLR GICD_CTLR macro
/linux-master/drivers/irqchip/
H A Dirq-gic-v3-its.c3030 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
3111 val = readl_relaxed(rbase + GICR_CTLR);
3186 val = readl_relaxed(rbase + GICR_CTLR);
3188 writel_relaxed(val, rbase + GICR_CTLR);
5221 val = readl_relaxed(rbase + GICR_CTLR);
5245 writel_relaxed(val, rbase + GICR_CTLR);
5247 /* Make sure any change to GICR_CTLR is observable by the GIC */
5251 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5255 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5267 * DEFINED whether GICR_CTLR
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H A Dirq-gic-v3.c1057 u32 ctlr = readl_relaxed(ptr + GICR_CTLR);
/linux-master/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v3.c651 REGISTER_DESC_WITH_LENGTH(GICR_CTLR,

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