Searched refs:FSIN (Results 1 - 25 of 28) sorted by relevance

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/freebsd-11-stable/contrib/one-true-awk/
H A Dawk.h123 #define FSIN 9 macro
H A Dlex.c79 { "sin", FSIN, BLTIN },
H A Drun.c1504 case FSIN:
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
H A DBasicTTIImpl.h1223 ISDs.push_back(ISD::FSIN);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp196 case ISD::FSIN: return "fsin";
H A DLegalizeFloatTypes.cpp117 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break;
1174 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break;
2120 case ISD::FSIN:
H A DLegalizeDAG.cpp2259 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2260 ? ISD::FCOS : ISD::FSIN;
3192 case ISD::FSIN:
3960 case ISD::FSIN:
4509 case ISD::FSIN:
H A DLegalizeVectorTypes.cpp96 case ISD::FSIN:
890 case ISD::FSIN:
2816 case ISD::FSIN:
H A DLegalizeVectorOps.cpp420 case ISD::FSIN:
H A DTargetLowering.cpp5601 case ISD::FSIN:
5717 case ISD::FSIN:
H A DSelectionDAGBuilder.cpp6185 case Intrinsic::sin: Opcode = ISD::FSIN; break;
7660 if (visitUnaryFloatCall(I, ISD::FSIN))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp145 setOperationAction(ISD::FSIN, MVT::f32, Custom);
488 case ISD::FSIN: return LowerTrig(Op, DAG);
775 case ISD::FSIN:
H A DAMDGPUISelLowering.cpp424 setOperationAction(ISD::FSIN, VT, Expand);
522 case ISD::FSIN:
3809 case ISD::FSIN:
H A DSIISelLowering.cpp441 setOperationAction(ISD::FSIN, MVT::f32, Custom);
503 setOperationAction(ISD::FSIN, MVT::f16, Promote);
4048 case ISD::FSIN:
7993 case ISD::FSIN:
8607 case ISD::FSIN:
8801 case ISD::FSIN:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1616 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1621 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1626 setOperationAction(ISD::FSIN , MVT::f32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp269 setOperationAction(ISD::FSIN, MVT::f128, Expand);
386 setOperationAction(ISD::FSIN, MVT::f32, Expand);
387 setOperationAction(ISD::FSIN, MVT::f64, Expand);
411 setOperationAction(ISD::FSIN, MVT::f16, Promote);
412 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
413 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
720 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
879 setOperationAction(ISD::FSIN, VT, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp94 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp290 setOperationAction(ISD::FSIN , MVT::f64, Expand);
295 setOperationAction(ISD::FSIN , MVT::f32, Expand);
666 setOperationAction(ISD::FSIN, VT, Expand);
960 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1022 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
1067 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp434 setOperationAction(ISD::FSIN, MVT::f32, Expand);
435 setOperationAction(ISD::FSIN, MVT::f64, Expand);
H A DMipsSEISelLowering.cpp149 setOperationAction(ISD::FSIN, MVT::f16, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp349 setOperationAction(ISD::FSIN, VT, Expand);
798 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
819 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
835 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
964 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1324 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1325 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1408 setOperationAction(ISD::FSIN, MVT::f16, Promote);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp164 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp572 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,

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