| /linux-master/drivers/gpu/drm/i915/ |
| H A D | intel_step.h | 46 func(E3) \
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| /linux-master/arch/m68k/fpsp040/ |
| H A D | x_unfl.S | 61 btstb #E3,E_BYTE(%a6)
95 btstb #E3,E_BYTE(%a6)
116 bclrb #E3,E_BYTE(%a6)
151 | If the exception bit set is E3, the exceptional operand from the
154 btstb #E3,E_BYTE(%a6)
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| H A D | skeleton.S | 84 | The provided code will clear the E3 exception (if pending),
145 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
182 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
208 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
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| H A D | gen_except.S | 168 | exception is to set the E1/E3 byte and clr the U flag.
170 | operr, and dz. commonE3 does this for E3 exceptions, which
182 bsetb #E3,E_BYTE(%a6) |set E3 flag
190 bsetb #E3,E_BYTE(%a6) |set E3 flag
300 bsetb #E3,E_BYTE(%a6) |set E3 flag
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| H A D | util.S | 103 btstb #E3,E_BYTE(%a6) |check for nu exception
328 | if E3
355 btstb #E3,E_BYTE(%a6)
423 btstb #E3,E_BYTE(%a6)
426 clrl %d0 |if E3, only opclass 0x0 is possible
436 | If E3, the format is extended.
444 btstb #E3,E_BYTE(%a6)
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| H A D | fpsp.h | 142 .set CMDREG3B,LV-48 | cmd reg for E3 exceptions (2 bytes)
189 .set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte)
191 .set E3,1 | which bit is E3 flag
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| H A D | round.S | 504 btstb #E3,E_BYTE(%a6) |test for type E3 exception
505 beqs not_E3 |not type E3 exception
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| H A D | x_store.S | 38 btstb #E3,E_BYTE(%a6)
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| /linux-master/lib/ |
| H A D | locking-selftest.c | 290 static void name##_123(void) { E1(); E2(); E3(); } \
291 static void name##_132(void) { E1(); E3(); E2(); } \
292 static void name##_213(void) { E2(); E1(); E3(); } \
293 static void name##_231(void) { E2(); E3(); E1(); } \
294 static void name##_312(void) { E3(); E1(); E2(); } \
295 static void name##_321(void) { E3(); E2(); E1(); }
924 #define E3() \ macro
956 #undef E3 macro
975 #define E3() \ macro
1006 #undef E3 macro
1038 #define E3 macro
1070 #undef E3 macro
1090 #define E3 macro
1102 #undef E3 macro
1122 #define E3 macro
1134 #undef E3 macro
1154 #define E3 macro
1166 #undef E3 macro
1186 #define E3 macro
1198 #undef E3 macro
1215 #define E3 macro
1245 #undef E3 macro
1265 #define E3 macro
1293 #undef E3 macro
1321 #define E3 macro
[all...] |
| /linux-master/drivers/pinctrl/aspeed/ |
| H A D | pinctrl-aspeed-g5.c | 1345 #define E3 181 macro
1346 SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
1347 SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5);
1348 PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5));
1349 FUNC_GROUP_DECL(ADC5, E3);
2008 ASPEED_PINCTRL_PIN(E3),
2575 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA
[all...] |
| H A D | pinctrl-aspeed-g4.c | 641 #define E3 80 macro
642 SIG_EXPR_LIST_DECL_SINGLE(E3, SCL5, I2C5, I2C5_DESC);
643 PIN_DECL_1(E3, GPIOK0, SCL5);
649 FUNC_GROUP_DECL(I2C5, E3, D2);
2015 ASPEED_PINCTRL_PIN(E3),
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| H A D | pinctrl-aspeed-g6.c | 1424 #define E3 227 macro
1425 SIG_EXPR_LIST_DECL_SESG(E3, RGMII2RXCTL, RGMII2, SIG_DESC_SET(SCU400, 19),
1427 PIN_DECL_1(E3, GPIO18C3, RGMII2RXCTL);
1457 FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
1823 ASPEED_PINCTRL_PIN(E3),
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| /linux-master/drivers/gpu/drm/amd/display/modules/color/ |
| H A D | color_gamma.c | 976 struct fixed31_32 E3; local
1040 E3 = dc_fixpt_add(E2, dc_fixpt_mul(min_lum_pq, temp2));
1041 compute_de_pq(E3, out_x);
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| /linux-master/drivers/media/tuners/ |
| H A D | mxl5005s.c | 2312 u32 divider_val, E3, E4, E5, E5A; local
2623 /* Equation E3 RFSYN_VCO_BIAS */
2624 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2625 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
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| /linux-master/drivers/pinctrl/ |
| H A D | pinctrl-pic32.c | 142 PINCTRL_PIN(67, "E3"),
221 "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
255 "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
260 "D9", "G6", "B8", "B15", "D4", "B0", "E3", "B7",
1209 PIC32_PINCTRL_GROUP(67, E3,
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