Searched refs:DP_MSE_SAT_UPDATE (Results 1 - 8 of 8) sorted by relevance
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dio_link_encoder.h | 49 SRI(DP_MSE_SAT_UPDATE, DP, id), \
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_dio_link_encoder.h | 50 SRI(DP_MSE_SAT_UPDATE, DP, id), \
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| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.h | 67 SRI(DP_MSE_SAT_UPDATE, DP, id), \
100 SRI(DP_MSE_SAT_UPDATE, DP, id), \
177 uint32_t DP_MSE_SAT_UPDATE; member in struct:dce110_link_enc_registers
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| H A D | dce_link_encoder.c | 1581 /* DP_MSE_SAT_UPDATE:
1586 REG_UPDATE(DP_MSE_SAT_UPDATE,
1587 DP_MSE_SAT_UPDATE, 1);
1590 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1602 REG_READ(DP_MSE_SAT_UPDATE);
1604 REG_GET(DP_MSE_SAT_UPDATE,
1605 DP_MSE_SAT_UPDATE, &value1);
1607 REG_GET(DP_MSE_SAT_UPDATE,
1610 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_link_encoder.h | 60 SRI(DP_MSE_SAT_UPDATE, DP, id), \
102 uint32_t DP_MSE_SAT_UPDATE; member in struct:dcn10_link_enc_registers
222 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
272 type DP_MSE_SAT_UPDATE;\
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| H A D | dcn10_link_encoder.c | 1302 /* DP_MSE_SAT_UPDATE:
1307 REG_UPDATE(DP_MSE_SAT_UPDATE,
1308 DP_MSE_SAT_UPDATE, 1);
1311 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1323 REG_READ(DP_MSE_SAT_UPDATE);
1325 REG_GET(DP_MSE_SAT_UPDATE,
1326 DP_MSE_SAT_UPDATE, &value1);
1328 REG_GET(DP_MSE_SAT_UPDATE,
1331 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
| H A D | dcn35_dio_link_encoder.h | 81 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.h | 325 SRI_ARR(DP_MSE_SAT2, DP, id), SRI_ARR(DP_MSE_SAT_UPDATE, DP, id), \
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