Searched refs:DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c44 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
45 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1299 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
[all...]
H A Ddcn_3_1_5_sh_mask.h3539 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
3529 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK macro
[all...]
H A Ddcn_2_0_0_sh_mask.h2365 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
[all...]
H A Ddcn_2_1_0_sh_mask.h2097 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
[all...]
H A Ddcn_1_0_sh_mask.h3596 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
[all...]
H A Ddcn_3_1_4_sh_mask.h10335 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK macro
[all...]
H A Ddcn_3_1_2_sh_mask.h5588 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
5576 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK macro
[all...]
H A Ddcn_3_0_1_sh_mask.h2254 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
[all...]
H A Ddcn_3_0_0_sh_mask.h2240 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L
2235 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK macro
[all...]
H A Ddcn_3_0_2_sh_mask.h2168 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
[all...]
H A Ddcn_3_1_6_sh_mask.h6183 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
[all...]

Completed in 9469 milliseconds