Searched refs:DIG_FIFO_CTRL0 (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_link_encoder.h33 SRI(DIG_FIFO_CTRL0, DIG, id)
H A Ddcn32_dio_stream_encoder.c353 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
355 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);
357 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);
359 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);
361 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
363 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
425 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0);
434 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);
438 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
447 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVE
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c58 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);
62 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
71 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
76 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
83 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);
419 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0);
H A Ddcn314_dio_stream_encoder.h110 SRI(DIG_FIFO_CTRL0, DIG, id)
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dio_stream_encoder.c419 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);
423 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000);
432 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);
441 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);
448 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);
H A Ddcn35_dio_stream_encoder.h111 SRI(DIG_FIFO_CTRL0, DIG, id),\
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h142 SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_link_encoder.h170 uint32_t DIG_FIFO_CTRL0; member in struct:dcn10_link_enc_registers
H A Ddcn10_stream_encoder.h190 uint32_t DIG_FIFO_CTRL0; member in struct:dcn10_stream_enc_registers
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h300 SRI_ARR(DIG_FIFO_CTRL0, DIG, id)

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