Searched refs:DCE_BASE (Results 1 - 5 of 5) sorted by relevance
| /linux-master/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_services.h | 152 dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
155 dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
158 generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \
162 generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vega10_reg_init.c | 45 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
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| H A D | vega20_reg_init.c | 44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
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| /linux-master/drivers/gpu/drm/amd/include/ |
| H A D | vega20_ip_offset.h | 49 static const struct IP_BASE DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | vega10_ip_offset.h | 46 static const struct IP_BASE __maybe_unused DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, variable in typeref:struct:__maybe_unused
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