Searched refs:CLK_SET_RATE_PARENT (Results 1 - 25 of 392) sorted by relevance

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/linux-master/drivers/clk/hisilicon/
H A Dclk-hi3670.c81 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x0, 3, 0, },
85 CLK_SET_RATE_PARENT, 0x0, 27, 0, },
87 CLK_SET_RATE_PARENT, 0x460, 16, 0, },
89 CLK_SET_RATE_PARENT, 0x460, 18, 0, },
91 CLK_SET_RATE_PARENT, 0x460, 20, 0, },
93 CLK_SET_RATE_PARENT, 0x410, 27, 0, },
95 CLK_SET_RATE_PARENT, 0x410, 28, 0, },
97 CLK_SET_RATE_PARENT, 0x410, 26, 0, },
99 CLK_SET_RATE_PARENT,
[all...]
H A Dclk-hi3660.c53 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
55 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
57 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
59 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
61 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
63 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
65 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
67 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
69 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
71 CLK_SET_RATE_PARENT,
[all...]
H A Dclk-hi6220.c52 { HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
53 { HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
54 { HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
55 { HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
56 { HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
57 { HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
58 { HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18, 0, },
59 { HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19, 0, },
60 { HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20, 0, },
61 { HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSE
[all...]
H A Dclk-hi3620.c85 { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0, 15, 2, 0, },
86 { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0, 17, 2, 0, },
87 { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0, 19, 2, 0, },
88 { HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0, 21, 2, 0, },
89 { HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x18, 0, 2, 0, },
90 { HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x18, 2, 2, 0, },
91 { HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x18, 4, 2, 0, },
92 { HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x18, 6, 2, 0, },
93 { HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x18, 8, 2, 0, },
94 { HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT,
[all...]
H A Dcrg-hi3798cv200.c76 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
79 CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
82 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
84 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
93 CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
96 CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
103 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
106 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
108 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
110 CLK_SET_RATE_PARENT,
[all...]
H A Dclk-hix5hd2.c60 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
62 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
64 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
67 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
73 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
75 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
78 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
80 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
82 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
85 CLK_SET_RATE_PARENT,
[all...]
H A Dcrg-hi3516cv300.c70 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
72 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
74 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
76 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
78 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
80 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
82 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
87 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
89 { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
91 { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
[all...]
H A Dclk-hi3559a.c142 CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
146 CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
150 CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
155 CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
160 CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table,
165 CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
170 CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table
175 CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table
180 CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table
187 CLK_SET_RATE_PARENT,
[all...]
H A Dclk-hi3519.c52 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
57 CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
59 CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
61 CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
63 CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
65 CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
67 CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
69 CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
71 CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
73 CLK_SET_RATE_PARENT,
[all...]
/linux-master/drivers/clk/mmp/
H A Dclk-of-pxa168.c125 CLK_SET_RATE_PARENT,
163 {0, "twsi0_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0, 4, 3, 0, &twsi0_lock},
164 {0, "twsi1_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1, 4, 3, 0, &twsi1_lock},
165 {0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3, 0, &kpc_lock},
166 {0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4, 3, 0, &pwm0_lock},
167 {0, "pwm1_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4, 3, 0, &pwm1_lock},
168 {0, "pwm2_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4, 3, 0, &pwm2_lock},
169 {0, "pwm3_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4, 3, 0, &pwm3_lock},
170 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
171 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART
[all...]
H A Dclk-of-mmp2.c175 {MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0, &acgr_lock},
176 {MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0, &acgr_lock},
201 CLK_SET_RATE_PARENT,
208 CLK_SET_RATE_PARENT,
213 CLK_SET_RATE_PARENT,
239 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
240 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
241 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
242 {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
243 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP
[all...]
H A Dclk-of-pxa1928.c80 CLK_SET_RATE_PARENT,
99 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
100 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
101 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock},
102 {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 4, 3, 0, &uart3_lock},
103 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 4, 3, 0, &ssp0_lock},
104 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 4, 3, 0, &ssp1_lock},
108 {PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
109 {PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
110 {PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI
[all...]
H A Dclk-of-pxa910.c105 CLK_SET_RATE_PARENT,
128 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
129 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
130 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
131 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
132 {0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER0, 4, 3, 0, &timer0_lock},
133 {0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER1, 4, 3, 0, &timer1_lock},
137 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
141 {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
142 {PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPI
[all...]
/linux-master/drivers/clk/rockchip/
H A Dclk-rk3308.c199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
223 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
231 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
235 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
[all...]
H A Dclk-px30.c209 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
213 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
217 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
221 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
225 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
229 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
233 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
237 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
241 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
245 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
[all...]
/linux-master/drivers/clk/qcom/
H A Ddispcc-sm8450.c257 .flags = CLK_SET_RATE_PARENT,
277 .flags = CLK_SET_RATE_PARENT,
292 .flags = CLK_SET_RATE_PARENT,
307 .flags = CLK_SET_RATE_PARENT,
330 .flags = CLK_SET_RATE_PARENT,
345 .flags = CLK_SET_RATE_PARENT,
360 .flags = CLK_SET_RATE_PARENT,
375 .flags = CLK_SET_RATE_PARENT,
390 .flags = CLK_SET_RATE_PARENT,
405 .flags = CLK_SET_RATE_PARENT,
[all...]
H A Dcamcc-sm8250.c89 .flags = CLK_SET_RATE_PARENT,
112 .flags = CLK_SET_RATE_PARENT,
163 .flags = CLK_SET_RATE_PARENT,
214 .flags = CLK_SET_RATE_PARENT,
265 .flags = CLK_SET_RATE_PARENT,
316 .flags = CLK_SET_RATE_PARENT,
413 .flags = CLK_SET_RATE_PARENT,
435 .flags = CLK_SET_RATE_PARENT,
456 .flags = CLK_SET_RATE_PARENT,
471 .flags = CLK_SET_RATE_PARENT,
[all...]
H A Ddispcc-sm8650.c291 .flags = CLK_SET_RATE_PARENT,
311 .flags = CLK_SET_RATE_PARENT,
326 .flags = CLK_SET_RATE_PARENT,
341 .flags = CLK_SET_RATE_PARENT,
364 .flags = CLK_SET_RATE_PARENT,
379 .flags = CLK_SET_RATE_PARENT,
394 .flags = CLK_SET_RATE_PARENT,
409 .flags = CLK_SET_RATE_PARENT,
424 .flags = CLK_SET_RATE_PARENT,
439 .flags = CLK_SET_RATE_PARENT,
[all...]
H A Ddispcc-sm8550.c293 .flags = CLK_SET_RATE_PARENT,
313 .flags = CLK_SET_RATE_PARENT,
328 .flags = CLK_SET_RATE_PARENT,
343 .flags = CLK_SET_RATE_PARENT,
366 .flags = CLK_SET_RATE_PARENT,
381 .flags = CLK_SET_RATE_PARENT,
396 .flags = CLK_SET_RATE_PARENT,
411 .flags = CLK_SET_RATE_PARENT,
426 .flags = CLK_SET_RATE_PARENT,
441 .flags = CLK_SET_RATE_PARENT,
[all...]
H A Ddispcc-x1e80100.c263 .flags = CLK_SET_RATE_PARENT,
283 .flags = CLK_SET_RATE_PARENT,
298 .flags = CLK_SET_RATE_PARENT,
313 .flags = CLK_SET_RATE_PARENT,
328 .flags = CLK_SET_RATE_PARENT,
343 .flags = CLK_SET_RATE_PARENT,
358 .flags = CLK_SET_RATE_PARENT,
373 .flags = CLK_SET_RATE_PARENT,
388 .flags = CLK_SET_RATE_PARENT,
403 .flags = CLK_SET_RATE_PARENT,
[all...]
H A Ddispcc-sc8280xp.c435 .flags = CLK_SET_RATE_PARENT,
449 .flags = CLK_SET_RATE_PARENT,
463 .flags = CLK_SET_RATE_PARENT,
477 .flags = CLK_SET_RATE_PARENT,
519 .flags = CLK_SET_RATE_PARENT,
533 .flags = CLK_SET_RATE_PARENT,
547 .flags = CLK_SET_RATE_PARENT,
561 .flags = CLK_SET_RATE_PARENT,
575 .flags = CLK_SET_RATE_PARENT,
589 .flags = CLK_SET_RATE_PARENT,
[all...]
H A Dcamcc-sm8450.c102 .flags = CLK_SET_RATE_PARENT,
125 .flags = CLK_SET_RATE_PARENT,
173 .flags = CLK_SET_RATE_PARENT,
244 .flags = CLK_SET_RATE_PARENT,
292 .flags = CLK_SET_RATE_PARENT,
340 .flags = CLK_SET_RATE_PARENT,
388 .flags = CLK_SET_RATE_PARENT,
436 .flags = CLK_SET_RATE_PARENT,
484 .flags = CLK_SET_RATE_PARENT,
612 .flags = CLK_SET_RATE_PARENT,
[all...]
/linux-master/drivers/clk/mxs/
H A Dclk.h41 return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT,
50 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
58 CLK_SET_RATE_PARENT, mult, div);
/linux-master/drivers/clk/samsung/
H A Dclk-exynos5410.c150 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
152 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
154 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
176 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
178 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
180 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
189 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
191 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
193 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
195 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT,
[all...]
/linux-master/drivers/clk/
H A Dclk-stm32f4.c435 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
557 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
560 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
562 { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
1179 CLK_SET_RATE_PARENT
1185 CLK_SET_RATE_PARENT
1191 CLK_SET_RATE_PARENT
1197 CLK_SET_RATE_PARENT
1206 CLK_SET_RATE_PARENT
1212 CLK_SET_RATE_PARENT
[all...]

Completed in 542 milliseconds

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