Lines Matching refs:CLK_SET_RATE_PARENT
150 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
152 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
154 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
176 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
178 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
180 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
189 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
191 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
193 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
195 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
198 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
216 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
218 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
220 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
222 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),