Searched refs:CFG_DRAM_INTERLEAVE (Results 1 - 16 of 16) sorted by relevance

/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm1250cpci/include/
H A Dbsp_config.h100 #define CFG_DRAM_INTERLEAVE 1 /* interleave the channels if possible */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125cpci/include/
H A Dbsp_config.h94 #define CFG_DRAM_INTERLEAVE 0 /* interleave the channels if possible */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125e/include/
H A Dbsp_config.h102 #define CFG_DRAM_INTERLEAVE 0 /* interleave the channels if possible */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125f/include/
H A Dbsp_config.h100 #define CFG_DRAM_INTERLEAVE 0 /* interleave the channels if possible */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125pcix/include/
H A Dbsp_config.h95 #define CFG_DRAM_INTERLEAVE 0 /* Can't interleave channels, there is only one */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/lausanne/include/
H A Dbsp_config.h101 #define CFG_DRAM_INTERLEAVE 0 /* interleave the channels if possible */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/include/
H A Dbsp_config.h100 #define CFG_DRAM_INTERLEAVE 1 /* interleave the channels if possible */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/vcs1280/include/
H A Dbsp_config.h101 #define CFG_DRAM_INTERLEAVE 0 macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/swarm/include/
H A Dbsp_config.h111 #define CFG_DRAM_INTERLEAVE 1 /* interleave the channels if possible */ macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91280e/include/
H A Dbsp_config.h123 #define CFG_DRAM_INTERLEAVE MC_FULLCHANINTLV macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480b/include/
H A Dbsp_config.h120 #define CFG_DRAM_INTERLEAVE MC_01CHANINTLV macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/include/
H A Dbsp_config.h119 #define CFG_DRAM_INTERLEAVE MC_NOCHANINTLV macro
/broadcom-cfe-1.4.2/cfe/arch/mips/board/vcs1280/src/
H A Dvcs1280_init.S146 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE)
/broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/src/
H A Dsentosa_init.S226 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE)
278 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE)
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm1250cpci/src/
H A Dbcm1250cpci_init.S285 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE)
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/
H A Dsb1250_draminit.c313 #ifndef CFG_DRAM_INTERLEAVE
314 #define CFG_DRAM_INTERLEAVE 0 macro
1362 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE), /* do port interleaving if possible */

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