Searched refs:BIT_1 (Results 1 - 25 of 38) sorted by relevance
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/linux-master/drivers/scsi/qla2xxx/ |
H A D | qla_edif.h | 20 #define EDIF_SA_CTL_FLG_DEL BIT_1 80 #define SA_FLAG_TX BIT_1 // 1=tx, 0=rx
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H A D | qla_nvme.h | 65 #define CF_READ_DATA BIT_1
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H A D | qla_fw.h | 30 #define PDO_FORCE_ADISC BIT_1 45 #define PDF_HARD_ADDR BIT_1 457 #define BD_READ_DATA BIT_1 498 #define CF_READ_DATA BIT_1 540 #define TMF_READ_DATA BIT_1 974 #define TCF_TARGET_RESET BIT_1 1001 #define AOF_NO_RRQ BIT_1 /* Do not send RRQ. */ 1195 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 1265 #define GPDX_DATA_INOUT (BIT_1|BIT_0) 1273 #define GPEX_ENABLE (BIT_1|BIT_ [all...] |
H A D | qla_def.h | 108 #define BIT_1 0x2 macro 230 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 250 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 416 #define SRB_GOT_BUF BIT_1 534 #define SRB_LOGIN_COND_PLOGI BIT_1 584 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 824 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 842 #define NVR_SELECT BIT_1 1099 #define MBX_DMA_OUT BIT_1 1112 #define MBX_DMA_OUT BIT_1 [all...] |
H A D | qla_tmpl.h | 61 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
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H A D | qla_target.h | 225 #define ATIO_EXEC_READ BIT_1 422 #define EF_NEW_SA BIT_1 483 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */ 841 TRC_DO_WORK = BIT_1, 967 #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
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H A D | qla_init.c | 4480 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 4484 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4494 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 4495 (tx_sens & (BIT_1 | BIT_0)); 4500 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 4502 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4512 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 4513 (tx_sens & (BIT_1 | BIT_0)); 4824 mid_init_cb->options = cpu_to_le16(BIT_1); 5255 nv->firmware_options[0] = BIT_2 | BIT_1; [all...] |
H A D | qla_mbx.c | 794 ha->max_supported_speed = mcp->mb[2] & (BIT_0|BIT_1); 801 (BIT_0 | BIT_1 | BIT_2); 1896 mcp->mb[1] |= BIT_1; 2399 mcp->mb[1] = BIT_1; 2532 if (opt & BIT_1) 2592 mb[1] |= BIT_1; 2601 mb[10] |= BIT_1; /* Class 3. */ 3137 * BIT_1 = mailbox error. 4338 rval = BIT_1; 4341 rval = BIT_1; [all...] |
H A D | qla_inline.h | 387 RESOURCE_EXCH = BIT_1, /* exchange */
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H A D | qla_gbl.h | 997 #define QLA2XX_SHT_LNK_DWN BIT_1
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H A D | qla_mid.c | 883 options |= BIT_1;
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/linux-master/drivers/scsi/ |
H A D | qla1280.h | 18 #define BIT_1 0x2 macro 120 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */ 134 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */ 141 #define PCI_INT BIT_1 /* PCI interrupt */ 146 #define NV_SELECT BIT_1 158 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */ 175 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */ 567 #define RF_FULL BIT_1 /* Full */ 965 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
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H A D | qla1280.c | 1116 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; 1682 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); 1696 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0) 1700 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0) 1824 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); 1834 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); 1901 BIT_3 | BIT_2 | BIT_1 | BIT_0, 1915 BIT_3 | BIT_2 | BIT_1 | BIT_0, 2135 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); 2208 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_ [all...] |
/linux-master/drivers/net/ethernet/qlogic/qlcnic/ |
H A D | qlcnic_hw.h | 140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
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H A D | qlcnic_hdr.h | 196 #define BIT_1 0x2 macro 493 #define TA_CTL_ENABLE BIT_1
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H A D | qlcnic_ctx.c | 1352 arg2 |= (BIT_0 | BIT_1); 1364 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); 1365 if (!(esw_cfg->offload_flags & BIT_1))
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H A D | qlcnic_83xx_hw.h | 531 #define QLC_REGISTER_DCB_AEN BIT_1
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H A D | qlcnic_minidump.c | 24 #define QLCNIC_DUMP_RWCRB BIT_1 753 if (dma_sts & BIT_1)
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H A D | qlcnic.h | 913 #define QLCNIC_FW_CAPABILITY_TSO BIT_1 929 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1 1315 #define QLCNIC_SWITCH_ENABLE BIT_1
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H A D | qlcnic_hw.c | 815 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9) 1033 if (!(offload_flags & BIT_1))
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H A D | qlcnic_sriov_pf.c | 390 cmd.req.arg[1] = ((func & 0xf) << 2) | BIT_6 | BIT_1; 703 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8;
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H A D | qlcnic_83xx_hw.c | 2022 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); 3538 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); 3569 #define QLCNIC_83XX_ADD_PORT1 BIT_1
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/linux-master/drivers/scsi/qla4xxx/ |
H A D | ql4_def.h | 81 #define BIT_1 0x2 macro
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H A D | ql4_os.c | 3547 sess->erl |= BIT_1; 3560 conn->tcp_timer_scale |= BIT_1; 3677 SET_BITVAL(sess->erl & BIT_1, options, BIT_1); 3686 SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2); 3687 SET_BITVAL(conn->tcp_timer_scale & BIT_0, options, BIT_1); 3783 sess->erl |= BIT_1; 3796 conn->tcp_timer_scale |= BIT_1; 8906 if (PCI_FUNC(ha->pdev->devfn) & BIT_1)
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H A D | ql4_fw.h | 61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */
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