159765Sjlemon/* SPDX-License-Identifier: GPL-2.0-only */ 259765Sjlemon/* 359765Sjlemon * Marvell Fibre Channel HBA Driver 459765Sjlemon * Copyright (c) 2021 Marvell 559765Sjlemon */ 659765Sjlemon#ifndef __QLA_EDIF_H 759765Sjlemon#define __QLA_EDIF_H 859765Sjlemon 959765Sjlemonstruct qla_scsi_host; 1059765Sjlemon#define EDIF_APP_ID 0x73730001 1159765Sjlemon 1259765Sjlemon#define EDIF_MAX_INDEX 2048 1359765Sjlemonstruct edif_sa_ctl { 1459765Sjlemon struct list_head next; 1559765Sjlemon uint16_t del_index; 1659765Sjlemon uint16_t index; 1759765Sjlemon uint16_t slot; 1859765Sjlemon uint16_t flags; 1959765Sjlemon#define EDIF_SA_CTL_FLG_REPL BIT_0 2059765Sjlemon#define EDIF_SA_CTL_FLG_DEL BIT_1 2159765Sjlemon#define EDIF_SA_CTL_FLG_CLEANUP_DEL BIT_4 2259765Sjlemon // Invalidate Index bit and mirrors QLA_SA_UPDATE_FLAGS_DELETE 2359765Sjlemon unsigned long state; 2459765Sjlemon#define EDIF_SA_CTL_USED 1 /* Active Sa update */ 2559765Sjlemon#define EDIF_SA_CTL_PEND 2 /* Waiting for slot */ 2684221Sdillon#define EDIF_SA_CTL_REPL 3 /* Active Replace and Delete */ 2784221Sdillon#define EDIF_SA_CTL_DEL 4 /* Delete Pending */ 2884221Sdillon struct fc_port *fcport; 2984221Sdillon struct bsg_job *bsg_job; 3059765Sjlemon struct qla_sa_update_frame sa_frame; 3159765Sjlemon}; 3259765Sjlemon 3359765Sjlemonenum enode_flags_t { 3459765Sjlemon ENODE_ACTIVE = 0x1, 3559765Sjlemon}; 3659765Sjlemon 3759765Sjlemonstruct pur_core { 3859765Sjlemon enum enode_flags_t enode_flags; 3959765Sjlemon spinlock_t pur_lock; 4059765Sjlemon struct list_head head; 4159765Sjlemon}; 4259765Sjlemon 4359765Sjlemonenum db_flags_t { 4459765Sjlemon EDB_ACTIVE = BIT_0, 4559765Sjlemon}; 4659765Sjlemon 4759765Sjlemon#define DBELL_ACTIVE(_v) (_v->e_dbell.db_flags & EDB_ACTIVE) 4859765Sjlemon#define DBELL_INACTIVE(_v) (!(_v->e_dbell.db_flags & EDB_ACTIVE)) 4959765Sjlemon 5059765Sjlemonstruct edif_dbell { 5159765Sjlemon enum db_flags_t db_flags; 5259765Sjlemon spinlock_t db_lock; 5359765Sjlemon struct list_head head; 5459765Sjlemon struct bsg_job *dbell_bsg_job; 5559765Sjlemon unsigned long bsg_expire; 5659765Sjlemon}; 5759765Sjlemon 5859765Sjlemon#define SA_UPDATE_IOCB_TYPE 0x71 /* Security Association Update IOCB entry */ 5959765Sjlemonstruct sa_update_28xx { 6059765Sjlemon uint8_t entry_type; /* Entry type. */ 6159765Sjlemon uint8_t entry_count; /* Entry count. */ 6259765Sjlemon uint8_t sys_define; /* System Defined. */ 6359765Sjlemon uint8_t entry_status; /* Entry Status. */ 6459765Sjlemon 6559765Sjlemon uint32_t handle; /* IOCB System handle. */ 6659765Sjlemon 6759765Sjlemon union { 6859765Sjlemon __le16 nport_handle; /* in: N_PORT handle. */ 6959765Sjlemon __le16 comp_sts; /* out: completion status */ 7059765Sjlemon#define CS_PORT_EDIF_UNAVAIL 0x28 7159765Sjlemon#define CS_PORT_EDIF_LOGOUT 0x29 7259765Sjlemon#define CS_PORT_EDIF_SUPP_NOT_RDY 0x64 7359765Sjlemon#define CS_PORT_EDIF_INV_REQ 0x66 7459765Sjlemon } u; 7559765Sjlemon uint8_t vp_index; 7659765Sjlemon uint8_t reserved_1; 7759765Sjlemon uint8_t port_id[3]; 7859765Sjlemon uint8_t flags; 7959765Sjlemon#define SA_FLAG_INVALIDATE BIT_0 8059765Sjlemon#define SA_FLAG_TX BIT_1 // 1=tx, 0=rx 8159765Sjlemon 8259765Sjlemon uint8_t sa_key[32]; /* 256 bit key */ 8359765Sjlemon __le32 salt; 8459765Sjlemon __le32 spi; 8559765Sjlemon uint8_t sa_control; 8659765Sjlemon#define SA_CNTL_ENC_FCSP (1 << 3) 8759765Sjlemon#define SA_CNTL_ENC_OPD (2 << 3) 8859765Sjlemon#define SA_CNTL_ENC_MSK (3 << 3) // mask bits 4,3 8959765Sjlemon#define SA_CNTL_AES_GMAC (1 << 2) 9059765Sjlemon#define SA_CNTL_KEY256 (2 << 0) 9159765Sjlemon#define SA_CNTL_KEY128 0 9259765Sjlemon 9359765Sjlemon uint8_t reserved_2; 9459765Sjlemon __le16 sa_index; // reserve: bit 11-15 9559765Sjlemon __le16 old_sa_info; 9659765Sjlemon __le16 new_sa_info; 9759765Sjlemon}; 9859765Sjlemon 9959765Sjlemon#define NUM_ENTRIES 256 10059765Sjlemon#define PUR_GET 1 10159765Sjlemon 10259765Sjlemonstruct dinfo { 10359765Sjlemon int nodecnt; 10459765Sjlemon int lstate; 10559765Sjlemon}; 10659765Sjlemon 10759765Sjlemonstruct pur_ninfo { 10859765Sjlemon port_id_t pur_sid; 10959765Sjlemon port_id_t pur_did; 11059765Sjlemon uint8_t vp_idx; 11159765Sjlemon short pur_bytes_rcvd; 11259765Sjlemon unsigned short pur_nphdl; 11359765Sjlemon unsigned int pur_rx_xchg_address; 11459765Sjlemon}; 11559765Sjlemon 11659765Sjlemonstruct purexevent { 11759765Sjlemon struct pur_ninfo pur_info; 11859765Sjlemon unsigned char *msgp; 11959765Sjlemon u32 msgp_len; 12059765Sjlemon}; 12159765Sjlemon 12259765Sjlemon#define N_UNDEF 0 12359765Sjlemon#define N_PUREX 1 12459765Sjlemonstruct enode { 12559765Sjlemon struct list_head list; 12659765Sjlemon struct dinfo dinfo; 12759765Sjlemon uint32_t ntype; 12859765Sjlemon union { 12959765Sjlemon struct purexevent purexinfo; 13059765Sjlemon } u; 13159765Sjlemon}; 13259765Sjlemon 13359765Sjlemon#define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES)) 13459765Sjlemon 13559765Sjlemon#define EDIF_SESSION_DOWN(_s) \ 13659765Sjlemon (qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \ 13759765Sjlemon _s->disc_state == DSC_DELETED || \ 13859765Sjlemon !_s->edif.app_sess_online)) 13959765Sjlemon 14059765Sjlemon#define EDIF_NEGOTIATION_PENDING(_fcport) \ 14159765Sjlemon (DBELL_ACTIVE(_fcport->vha) && \ 14259765Sjlemon (_fcport->disc_state == DSC_LOGIN_AUTH_PEND)) 14359765Sjlemon 14459765Sjlemon#define EDIF_SESS_DELETE(_s) \ 14559765Sjlemon (qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \ 14659765Sjlemon _s->disc_state == DSC_DELETED)) 14759765Sjlemon 14859765Sjlemon#define EDIF_CAP(_ha) (ql2xsecenable && IS_QLA28XX(_ha)) 14959765Sjlemon 15059765Sjlemon#endif /* __QLA_EDIF_H */ 15159765Sjlemon