Searched refs:AR_PCU_MISC (Results 1 - 7 of 7) sorted by relevance

/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_recv.c271 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
273 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
H A Dar9300_keycache.c421 val = OS_REG_READ(ah, AR_PCU_MISC);
427 OS_REG_WRITE(ah, AR_PCU_MISC, val);
H A Dar9300_xmit.c875 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
936 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
H A Dar9300_misc.c973 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
1056 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1059 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
2564 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2602 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2604 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
H A Dar9300_reset.c4249 AR_PCU_MISC, OS_REG_READ(ah, AR_PCU_MISC) | ahp->ah_misc_mode);
4252 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
H A Dar9300_mci.c1057 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
H A Dar9300reg.h1728 #define AR_PCU_MISC AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE) macro

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