1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_desc.h" 21#include "ah_internal.h" 22 23#include "ar9300/ar9300.h" 24#include "ar9300/ar9300reg.h" 25#include "ar9300/ar9300phy.h" 26#include "ar9300/ar9300desc.h" 27 28#define TU_TO_USEC(_tu) ((_tu) << 10) 29#define ONE_EIGHTH_TU_TO_USEC(_tu8) ((_tu8) << 7) 30 31/* 32 * Update Tx FIFO trigger level. 33 * 34 * Set b_inc_trig_level to TRUE to increase the trigger level. 35 * Set b_inc_trig_level to FALSE to decrease the trigger level. 36 * 37 * Returns TRUE if the trigger level was updated 38 */ 39HAL_BOOL 40ar9300_update_tx_trig_level(struct ath_hal *ah, HAL_BOOL b_inc_trig_level) 41{ 42 struct ath_hal_9300 *ahp = AH9300(ah); 43 u_int32_t txcfg, cur_level, new_level; 44 HAL_INT omask; 45 46 if (AH9300(ah)->ah_tx_trig_level >= MAX_TX_FIFO_THRESHOLD && 47 b_inc_trig_level) 48 { 49 return AH_FALSE; 50 } 51 52 /* 53 * Disable interrupts while futzing with the fifo level. 54 */ 55 omask = ar9300_set_interrupts(ah, ahp->ah_mask_reg &~ HAL_INT_GLOBAL, 0); 56 57 txcfg = OS_REG_READ(ah, AR_TXCFG); 58 cur_level = MS(txcfg, AR_FTRIG); 59 new_level = cur_level; 60 61 if (b_inc_trig_level) { /* increase the trigger level */ 62 if (cur_level < MAX_TX_FIFO_THRESHOLD) { 63 new_level++; 64 } 65 } else if (cur_level > MIN_TX_FIFO_THRESHOLD) { 66 new_level--; 67 } 68 69 if (new_level != cur_level) { 70 /* Update the trigger level */ 71 OS_REG_WRITE(ah, 72 AR_TXCFG, (txcfg &~ AR_FTRIG) | SM(new_level, AR_FTRIG)); 73 } 74 75 /* re-enable chip interrupts */ 76 ar9300_set_interrupts(ah, omask, 0); 77 78 AH9300(ah)->ah_tx_trig_level = new_level; 79 80 return (new_level != cur_level); 81} 82 83/* 84 * Returns the value of Tx Trigger Level 85 */ 86u_int16_t 87ar9300_get_tx_trig_level(struct ath_hal *ah) 88{ 89 return (AH9300(ah)->ah_tx_trig_level); 90} 91 92/* 93 * Set the properties of the tx queue with the parameters 94 * from q_info. 95 */ 96HAL_BOOL 97ar9300_set_tx_queue_props(struct ath_hal *ah, int q, const HAL_TXQ_INFO *q_info) 98{ 99 struct ath_hal_9300 *ahp = AH9300(ah); 100 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 101 102 if (q >= p_cap->halTotalQueues) { 103 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 104 return AH_FALSE; 105 } 106 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], q_info); 107} 108 109/* 110 * Return the properties for the specified tx queue. 111 */ 112HAL_BOOL 113ar9300_get_tx_queue_props(struct ath_hal *ah, int q, HAL_TXQ_INFO *q_info) 114{ 115 struct ath_hal_9300 *ahp = AH9300(ah); 116 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 117 118 119 if (q >= p_cap->halTotalQueues) { 120 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 121 return AH_FALSE; 122 } 123 return ath_hal_getTxQProps(ah, q_info, &ahp->ah_txq[q]); 124} 125 126enum { 127 AH_TX_QUEUE_MINUS_OFFSET_BEACON = 1, 128 AH_TX_QUEUE_MINUS_OFFSET_CAB = 2, 129 AH_TX_QUEUE_MINUS_OFFSET_UAPSD = 3, 130 AH_TX_QUEUE_MINUS_OFFSET_PAPRD = 4, 131}; 132 133/* 134 * Allocate and initialize a tx DCU/QCU combination. 135 */ 136int 137ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, 138 const HAL_TXQ_INFO *q_info) 139{ 140 struct ath_hal_9300 *ahp = AH9300(ah); 141 HAL_TX_QUEUE_INFO *qi; 142 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 143 int q; 144 145 /* XXX move queue assignment to driver */ 146 switch (type) { 147 case HAL_TX_QUEUE_BEACON: 148 /* highest priority */ 149 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_BEACON; 150 break; 151 case HAL_TX_QUEUE_CAB: 152 /* next highest priority */ 153 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_CAB; 154 break; 155 case HAL_TX_QUEUE_UAPSD: 156 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_UAPSD; 157 break; 158 case HAL_TX_QUEUE_PAPRD: 159 q = p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; 160 break; 161 case HAL_TX_QUEUE_DATA: 162 /* 163 * don't infringe on top 4 queues, reserved for: 164 * beacon, CAB, UAPSD, PAPRD 165 */ 166 for (q = 0; 167 q < p_cap->halTotalQueues - AH_TX_QUEUE_MINUS_OFFSET_PAPRD; 168 q++) 169 { 170 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) { 171 break; 172 } 173 } 174 if (q == p_cap->halTotalQueues - 3) { 175 HALDEBUG(ah, HAL_DEBUG_QUEUE, 176 "%s: no available tx queue\n", __func__); 177 return -1; 178 } 179 break; 180 default: 181 HALDEBUG(ah, HAL_DEBUG_QUEUE, 182 "%s: bad tx queue type %u\n", __func__, type); 183 return -1; 184 } 185 186 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: queue %u\n", __func__, q); 187 188 qi = &ahp->ah_txq[q]; 189 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) { 190 HALDEBUG(ah, HAL_DEBUG_QUEUE, 191 "%s: tx queue %u already active\n", __func__, q); 192 return -1; 193 } 194 195 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO)); 196 qi->tqi_type = type; 197 198 if (q_info == AH_NULL) { 199 /* by default enable OK+ERR+DESC+URN interrupts */ 200 qi->tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 201 | HAL_TXQ_TXERRINT_ENABLE 202 | HAL_TXQ_TXDESCINT_ENABLE 203 | HAL_TXQ_TXURNINT_ENABLE; 204 qi->tqi_aifs = INIT_AIFS; 205 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */ 206 qi->tqi_cwmax = INIT_CWMAX; 207 qi->tqi_shretry = INIT_SH_RETRY; 208 qi->tqi_lgretry = INIT_LG_RETRY; 209 qi->tqi_physCompBuf = 0; 210 } else { 211 qi->tqi_physCompBuf = q_info->tqi_compBuf; 212 (void) ar9300_set_tx_queue_props(ah, q, q_info); 213 } 214 /* NB: must be followed by ar9300_reset_tx_queue */ 215 return q; 216} 217 218/* 219 * Update the h/w interrupt registers to reflect a tx q's configuration. 220 */ 221static void 222set_tx_q_interrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi) 223{ 224 struct ath_hal_9300 *ahp = AH9300(ah); 225 226 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, 227 "%s: tx ok 0x%x err 0x%x eol 0x%x urn 0x%x\n", 228 __func__, 229 ahp->ah_tx_ok_interrupt_mask, 230 ahp->ah_tx_err_interrupt_mask, 231 ahp->ah_tx_eol_interrupt_mask, 232 ahp->ah_tx_urn_interrupt_mask); 233 234 OS_REG_WRITE(ah, AR_IMR_S0, 235 SM(ahp->ah_tx_ok_interrupt_mask, AR_IMR_S0_QCU_TXOK)); 236 OS_REG_WRITE(ah, AR_IMR_S1, 237 SM(ahp->ah_tx_err_interrupt_mask, AR_IMR_S1_QCU_TXERR) 238 | SM(ahp->ah_tx_eol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); 239 OS_REG_RMW_FIELD(ah, 240 AR_IMR_S2, AR_IMR_S2_QCU_TXURN, ahp->ah_tx_urn_interrupt_mask); 241 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2); 242} 243 244/* 245 * Free a tx DCU/QCU combination. 246 */ 247HAL_BOOL 248ar9300_release_tx_queue(struct ath_hal *ah, u_int q) 249{ 250 struct ath_hal_9300 *ahp = AH9300(ah); 251 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 252 HAL_TX_QUEUE_INFO *qi; 253 254 if (q >= p_cap->halTotalQueues) { 255 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 256 return AH_FALSE; 257 } 258 259 qi = &ahp->ah_txq[q]; 260 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 261 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); 262 return AH_FALSE; 263 } 264 265 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: release queue %u\n", __func__, q); 266 267 qi->tqi_type = HAL_TX_QUEUE_INACTIVE; 268 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); 269 ahp->ah_tx_err_interrupt_mask &= ~(1 << q); 270 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); 271 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); 272 set_tx_q_interrupts(ah, qi); 273 274 return AH_TRUE; 275} 276 277/* 278 * Set the retry, aifs, cwmin/max, ready_time regs for specified queue 279 * Assumes: 280 * phw_channel has been set to point to the current channel 281 */ 282HAL_BOOL 283ar9300_reset_tx_queue(struct ath_hal *ah, u_int q) 284{ 285 struct ath_hal_9300 *ahp = AH9300(ah); 286// struct ath_hal_private *ap = AH_PRIVATE(ah); 287 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 288 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 289 HAL_TX_QUEUE_INFO *qi; 290 u_int32_t cw_min, chan_cw_min, value; 291 uint32_t qmisc, dmisc; 292 293 if (q >= p_cap->halTotalQueues) { 294 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: invalid queue num %u\n", __func__, q); 295 return AH_FALSE; 296 } 297 298 qi = &ahp->ah_txq[q]; 299 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) { 300 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: inactive queue %u\n", __func__, q); 301 return AH_TRUE; /* XXX??? */ 302 } 303 304 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: reset queue %u\n", __func__, q); 305 306 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) { 307 /* 308 * Select cwmin according to channel type. 309 * NB: chan can be NULL during attach 310 */ 311 if (chan && IEEE80211_IS_CHAN_B(chan)) { 312 chan_cw_min = INIT_CWMIN_11B; 313 } else { 314 chan_cw_min = INIT_CWMIN; 315 } 316 /* make sure that the CWmin is of the form (2^n - 1) */ 317 for (cw_min = 1; cw_min < chan_cw_min; cw_min = (cw_min << 1) | 1) {} 318 } else { 319 cw_min = qi->tqi_cwmin; 320 } 321 322 /* set cw_min/Max and AIFS values */ 323 if (q > 3 || (!AH9300(ah)->ah_fccaifs)) 324 /* values should not be overwritten if domain is FCC and manual rate 325 less than 24Mb is set, this check is making sure this */ 326 { 327 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(cw_min, AR_D_LCL_IFS_CWMIN) 328 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) 329 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 330 } 331 332 /* Set retry limit values */ 333 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), 334 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | 335 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | 336 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); 337 338 /* enable early termination on the QCU */ 339 qmisc = AR_Q_MISC_DCU_EARLY_TERM_REQ; 340 341 /* enable DCU to wait for next fragment from QCU */ 342 if (AR_SREV_WASP(ah) && (AH_PRIVATE((ah))->ah_macRev <= AR_SREV_REVISION_WASP_12)) { 343 /* WAR for EV#85395: Wasp Rx overrun issue - reduces Tx queue backoff 344 * threshold to 1 to avoid Rx overruns - Fixed in Wasp 1.3 */ 345 dmisc = AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1; 346 } else { 347 dmisc = AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2; 348 } 349 350 /* multiqueue support */ 351 if (qi->tqi_cbrPeriod) { 352 OS_REG_WRITE(ah, 353 AR_QCBRCFG(q), 354 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | 355 SM(qi->tqi_cbrOverflowLimit, 356 AR_Q_CBRCFG_OVF_THRESH)); 357 qmisc |= AR_Q_MISC_FSP_CBR | 358 (qi->tqi_cbrOverflowLimit ? 359 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0); 360 } 361 362 if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) { 363 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 364 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | 365 AR_Q_RDYTIMECFG_EN); 366 } 367 368 OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | 369 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); 370 371 if (qi->tqi_readyTime && 372 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE)) 373 qmisc |= AR_Q_MISC_RDYTIME_EXP_POLICY; 374 if (qi->tqi_qflags & HAL_TXQ_DBA_GATED) 375 qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_DBA_GATED; 376 if (MS(qmisc, AR_Q_MISC_FSP) != AR_Q_MISC_FSP_ASAP) { 377 /* 378 * These are meangingful only when not scheduled asap. 379 */ 380 if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY) 381 qmisc |= AR_Q_MISC_CBR_INCR_DIS0; 382 else 383 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS0; 384 if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY) 385 qmisc |= AR_Q_MISC_CBR_INCR_DIS1; 386 else 387 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS1; 388 } 389 390 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE) 391 dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS; 392 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE) 393 dmisc |= AR_D_MISC_FRAG_BKOFF_EN; 394 if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL) 395 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 396 AR_D_MISC_ARB_LOCKOUT_CNTRL); 397 else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA) 398 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR, 399 AR_D_MISC_ARB_LOCKOUT_CNTRL); 400 if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL) 401 dmisc |= SM(AR_D_MISC_VIR_COL_HANDLING_IGNORE, 402 AR_D_MISC_VIR_COL_HANDLING); 403 if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS) 404 dmisc |= AR_D_MISC_SEQ_NUM_INCR_DIS; 405 406 switch (qi->tqi_type) { 407 case HAL_TX_QUEUE_BEACON: /* beacon frames */ 408 qmisc |= AR_Q_MISC_FSP_DBA_GATED 409 | AR_Q_MISC_BEACON_USE 410 | AR_Q_MISC_CBR_INCR_DIS1; 411 412 dmisc |= (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 413 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 414 | AR_D_MISC_BEACON_USE 415 | AR_D_MISC_POST_FR_BKOFF_DIS; 416 /* XXX cwmin and cwmax should be 0 for beacon queue */ 417 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS) { 418 OS_REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) 419 | SM(0, AR_D_LCL_IFS_CWMAX) 420 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 421 } 422 break; 423 case HAL_TX_QUEUE_CAB: /* CAB frames */ 424 /* 425 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY, 426 * bug #6079. There is an issue with the CAB Queue 427 * not properly refreshing the Tx descriptor if 428 * the TXE clear setting is used. 429 */ 430 qmisc |= AR_Q_MISC_FSP_DBA_GATED 431 | AR_Q_MISC_CBR_INCR_DIS1 432 | AR_Q_MISC_CBR_INCR_DIS0; 433 434 if (qi->tqi_readyTime) { 435 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 436 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | 437 AR_Q_RDYTIMECFG_EN); 438 } else { 439 440 value = (ahp->ah_beaconInterval * 50 / 100) 441 - ah->ah_config.ah_additional_swba_backoff 442 - ah->ah_config.ah_sw_beacon_response_time 443 + ah->ah_config.ah_dma_beacon_response_time; 444 /* 445 * XXX Ensure it isn't too low - nothing lower 446 * XXX than 10 TU 447 */ 448 if (value < 10) 449 value = 10; 450 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, 451 "%s: defaulting to rdytime = %d uS\n", 452 __func__, value); 453 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), 454 SM(TU_TO_USEC(value), AR_Q_RDYTIMECFG_DURATION) | 455 AR_Q_RDYTIMECFG_EN); 456 } 457 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 458 AR_D_MISC_ARB_LOCKOUT_CNTRL); 459 break; 460 case HAL_TX_QUEUE_PSPOLL: 461 /* 462 * We may configure ps_poll QCU to be TIM-gated in the 463 * future; TIM_GATED bit is not enabled currently because 464 * of a hardware problem in Oahu that overshoots the TIM 465 * bitmap in beacon and may find matching associd bit in 466 * non-TIM elements and send PS-poll PS poll processing 467 * will be done in software 468 */ 469 qmisc |= AR_Q_MISC_CBR_INCR_DIS1; 470 break; 471 case HAL_TX_QUEUE_UAPSD: 472 dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS; 473 break; 474 default: /* NB: silence compiler */ 475 break; 476 } 477 478#ifndef AH_DISABLE_WME 479 /* 480 * Yes, this is a hack and not the right way to do it, but 481 * it does get the lockout bits and backoff set for the 482 * high-pri WME queues for testing. We need to either extend 483 * the meaning of queue_info->mode, or create something like 484 * queue_info->dcumode. 485 */ 486 if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) { 487 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 488 AR_D_MISC_ARB_LOCKOUT_CNTRL) | 489 AR_D_MISC_POST_FR_BKOFF_DIS; 490 } 491#endif 492 493 OS_REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); 494 OS_REG_WRITE(ah, AR_QMISC(q), qmisc); 495 OS_REG_WRITE(ah, AR_DMISC(q), dmisc); 496 497 /* 498 * Always update the secondary interrupt mask registers - this 499 * could be a new queue getting enabled in a running system or 500 * hw getting re-initialized during a reset! 501 * 502 * Since we don't differentiate between tx interrupts corresponding 503 * to individual queues - secondary tx mask regs are always unmasked; 504 * tx interrupts are enabled/disabled for all queues collectively 505 * using the primary mask reg 506 */ 507 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE) { 508 ahp->ah_tx_ok_interrupt_mask |= (1 << q); 509 } else { 510 ahp->ah_tx_ok_interrupt_mask &= ~(1 << q); 511 } 512 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE) { 513 ahp->ah_tx_err_interrupt_mask |= (1 << q); 514 } else { 515 ahp->ah_tx_err_interrupt_mask &= ~(1 << q); 516 } 517 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE) { 518 ahp->ah_tx_eol_interrupt_mask |= (1 << q); 519 } else { 520 ahp->ah_tx_eol_interrupt_mask &= ~(1 << q); 521 } 522 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE) { 523 ahp->ah_tx_urn_interrupt_mask |= (1 << q); 524 } else { 525 ahp->ah_tx_urn_interrupt_mask &= ~(1 << q); 526 } 527 set_tx_q_interrupts(ah, qi); 528 529 return AH_TRUE; 530} 531 532/* 533 * Get the TXDP for the specified queue 534 */ 535u_int32_t 536ar9300_get_tx_dp(struct ath_hal *ah, u_int q) 537{ 538 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 539 return OS_REG_READ(ah, AR_QTXDP(q)); 540} 541 542/* 543 * Set the tx_dp for the specified queue 544 */ 545HAL_BOOL 546ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp) 547{ 548 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 549 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 550 HALASSERT(txdp != 0); 551 552 OS_REG_WRITE(ah, AR_QTXDP(q), txdp); 553 554 return AH_TRUE; 555} 556 557/* 558 * Transmit Enable is read-only now 559 */ 560HAL_BOOL 561ar9300_start_tx_dma(struct ath_hal *ah, u_int q) 562{ 563 return AH_TRUE; 564} 565 566/* 567 * Return the number of pending frames or 0 if the specified 568 * queue is stopped. 569 */ 570u_int32_t 571ar9300_num_tx_pending(struct ath_hal *ah, u_int q) 572{ 573 u_int32_t npend; 574 575 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); 576 577 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; 578 if (npend == 0) { 579 /* 580 * Pending frame count (PFC) can momentarily go to zero 581 * while TXE remains asserted. In other words a PFC of 582 * zero is not sufficient to say that the queue has stopped. 583 */ 584 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) { 585 npend = 1; /* arbitrarily return 1 */ 586 } 587 } 588#ifdef DEBUG 589 if (npend && (AH9300(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { 590 if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) { 591 HALDEBUG(ah, HAL_DEBUG_QUEUE, "RTSD on CAB queue\n"); 592 /* Clear the ready_time shutdown status bits */ 593 OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); 594 } 595 } 596#endif 597 HALASSERT((npend == 0) || 598 (AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE)); 599 600 return npend; 601} 602 603/* 604 * Stop transmit on the specified queue 605 */ 606HAL_BOOL 607ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout) 608{ 609 struct ath_hal_9300 *ahp = AH9300(ah); 610 611 /* 612 * If we call abort txdma instead, no need to stop RX. 613 * Otherwise, the RX logic might not be restarted properly. 614 */ 615 ahp->ah_abort_txdma_norx = AH_FALSE; 616 617 /* 618 * Directly call abort. It is better, hardware-wise, to stop all 619 * queues at once than individual ones. 620 */ 621 return ar9300_abort_tx_dma(ah); 622 623#if 0 624#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 625#define AH_TIME_QUANTUM 100 /* usec */ 626 u_int wait; 627 628 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 629 630 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 631 632 if (timeout == 0) { 633 timeout = AH_TX_STOP_DMA_TIMEOUT; 634 } 635 636 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 637 638 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 639 if (ar9300_num_tx_pending(ah, q) == 0) { 640 break; 641 } 642 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ 643 } 644 645#ifdef AH_DEBUG 646 if (wait == 0) { 647 HALDEBUG(ah, HAL_DEBUG_QUEUE, 648 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); 649 HALDEBUG(ah, HAL_DEBUG_QUEUE, 650 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", 651 __func__, 652 OS_REG_READ(ah, AR_QSTS(q)), 653 OS_REG_READ(ah, AR_Q_TXE), 654 OS_REG_READ(ah, AR_Q_TXD), 655 OS_REG_READ(ah, AR_QCBRCFG(q))); 656 HALDEBUG(ah, HAL_DEBUG_QUEUE, 657 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 658 __func__, 659 OS_REG_READ(ah, AR_QMISC(q)), 660 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 661 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 662 } 663#endif /* AH_DEBUG */ 664 665 /* 2413+ and up can kill packets at the PCU level */ 666 if (ar9300_num_tx_pending(ah, q)) { 667 u_int32_t tsf_low, j; 668 669 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", 670 __func__, ar9300_num_tx_pending(ah, q), q); 671 672 /* Kill last PCU Tx Frame */ 673 /* TODO - save off and restore current values of Q1/Q2? */ 674 for (j = 0; j < 2; j++) { 675 tsf_low = OS_REG_READ(ah, AR_TSF_L32); 676 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); 677 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 678 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); 679 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 680 681 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { 682 break; 683 } 684 685 HALDEBUG(ah, HAL_DEBUG_QUEUE, 686 "%s: TSF have moved while trying to set " 687 "quiet time TSF: 0x%08x\n", 688 __func__, tsf_low); 689 /* TSF shouldn't count twice or reg access is taking forever */ 690 HALASSERT(j < 1); 691 } 692 693 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 694 695 /* Allow the quiet mechanism to do its work */ 696 OS_DELAY(200); 697 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 698 699 /* Verify all transmit is dead */ 700 wait = timeout / AH_TIME_QUANTUM; 701 while (ar9300_num_tx_pending(ah, q)) { 702 if ((--wait) == 0) { 703 HALDEBUG(ah, HAL_DEBUG_TX, 704 "%s: Failed to stop Tx DMA in %d msec " 705 "after killing last frame\n", 706 __func__, timeout / 1000); 707 break; 708 } 709 OS_DELAY(AH_TIME_QUANTUM); 710 } 711 712 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 713 } 714 715 OS_REG_WRITE(ah, AR_Q_TXD, 0); 716 return (wait != 0); 717 718#undef AH_TX_STOP_DMA_TIMEOUT 719#undef AH_TIME_QUANTUM 720#endif 721} 722 723/* 724 * Really Stop transmit on the specified queue 725 */ 726HAL_BOOL 727ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout) 728{ 729#define AH_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 730#define AH_TIME_QUANTUM 100 /* usec */ 731 u_int wait; 732 733 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.hal_total_queues); 734 735 HALASSERT(AH9300(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); 736 737 if (timeout == 0) { 738 timeout = AH_TX_STOP_DMA_TIMEOUT; 739 } 740 741 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); 742 743 for (wait = timeout / AH_TIME_QUANTUM; wait != 0; wait--) { 744 if (ar9300_num_tx_pending(ah, q) == 0) { 745 break; 746 } 747 OS_DELAY(AH_TIME_QUANTUM); /* XXX get actual value */ 748 } 749 750#ifdef AH_DEBUG 751 if (wait == 0) { 752 HALDEBUG(ah, HAL_DEBUG_QUEUE, 753 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); 754 HALDEBUG(ah, HAL_DEBUG_QUEUE, 755 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", 756 __func__, 757 OS_REG_READ(ah, AR_QSTS(q)), 758 OS_REG_READ(ah, AR_Q_TXE), 759 OS_REG_READ(ah, AR_Q_TXD), 760 OS_REG_READ(ah, AR_QCBRCFG(q))); 761 HALDEBUG(ah, HAL_DEBUG_QUEUE, 762 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n", 763 __func__, 764 OS_REG_READ(ah, AR_QMISC(q)), 765 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), 766 OS_REG_READ(ah, AR_Q_RDYTIMESHDN)); 767 } 768#endif /* AH_DEBUG */ 769 770 /* 2413+ and up can kill packets at the PCU level */ 771 if (ar9300_num_tx_pending(ah, q)) { 772 u_int32_t tsf_low, j; 773 774 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: Num of pending TX Frames %d on Q %d\n", 775 __func__, ar9300_num_tx_pending(ah, q), q); 776 777 /* Kill last PCU Tx Frame */ 778 /* TODO - save off and restore current values of Q1/Q2? */ 779 for (j = 0; j < 2; j++) { 780 tsf_low = OS_REG_READ(ah, AR_TSF_L32); 781 OS_REG_WRITE(ah, AR_QUIET2, SM(10, AR_QUIET2_QUIET_DUR)); 782 OS_REG_WRITE(ah, AR_QUIET_PERIOD, 100); 783 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsf_low >> 10); 784 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 785 786 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsf_low >> 10)) { 787 break; 788 } 789 790 HALDEBUG(ah, HAL_DEBUG_QUEUE, 791 "%s: TSF have moved while trying to set " 792 "quiet time TSF: 0x%08x\n", 793 __func__, tsf_low); 794 /* TSF shouldn't count twice or reg access is taking forever */ 795 HALASSERT(j < 1); 796 } 797 798 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 799 800 /* Allow the quiet mechanism to do its work */ 801 OS_DELAY(200); 802 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 803 804 /* Verify all transmit is dead */ 805 wait = timeout / AH_TIME_QUANTUM; 806 while (ar9300_num_tx_pending(ah, q)) { 807 if ((--wait) == 0) { 808 HALDEBUG(ah, HAL_DEBUG_TX, 809 "%s: Failed to stop Tx DMA in %d msec " 810 "after killing last frame\n", 811 __func__, timeout / 1000); 812 break; 813 } 814 OS_DELAY(AH_TIME_QUANTUM); 815 } 816 817 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 818 } 819 820 OS_REG_WRITE(ah, AR_Q_TXD, 0); 821 return (wait != 0); 822 823#undef AH_TX_STOP_DMA_TIMEOUT 824#undef AH_TIME_QUANTUM 825} 826 827/* 828 * Abort transmit on all queues 829 */ 830#define AR9300_ABORT_LOOPS 1000 831#define AR9300_ABORT_WAIT 5 832#define NEXT_TBTT_NOW 10 833HAL_BOOL 834ar9300_abort_tx_dma(struct ath_hal *ah) 835{ 836 struct ath_hal_9300 *ahp = AH9300(ah); 837 int i, q; 838 u_int32_t nexttbtt, nextdba, tsf_tbtt, tbtt, dba; 839 HAL_BOOL stopped; 840 HAL_BOOL status = AH_TRUE; 841 842 if (ahp->ah_abort_txdma_norx) { 843 /* 844 * First of all, make sure RX has been stopped 845 */ 846 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) { 847 /* Need to stop RX DMA before reset otherwise chip might hang */ 848 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */ 849 ar9300_set_rx_filter(ah, 0); 850 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */ 851 if (!stopped) { 852 /* 853 * During the transition from full sleep to reset, 854 * recv DMA regs are not available to be read 855 */ 856 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 857 "%s[%d]: ar9300_stop_dma_receive failed\n", __func__, __LINE__); 858 //We still continue to stop TX dma 859 //return AH_FALSE; 860 } 861 } else { 862 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 863 "%s[%d]: Chip is already in full sleep\n", __func__, __LINE__); 864 } 865 } 866 867 /* 868 * set txd on all queues 869 */ 870 OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); 871 872 /* 873 * set tx abort bits (also disable rx) 874 */ 875 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 876 /* Add a new receipe from K31 code */ 877 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | 878 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR); 879 /* beacon Q flush */ 880 nexttbtt = OS_REG_READ(ah, AR_NEXT_TBTT_TIMER); 881 nextdba = OS_REG_READ(ah, AR_NEXT_DMA_BEACON_ALERT); 882 //printk("%s[%d]:dba: %d, nt: %d \n", __func__, __LINE__, nextdba, nexttbtt); 883 tsf_tbtt = OS_REG_READ(ah, AR_TSF_L32); 884 tbtt = tsf_tbtt + NEXT_TBTT_NOW; 885 dba = tsf_tbtt; 886 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, dba); 887 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, tbtt); 888 OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 889 890 /* 891 * Let TXE (all queues) clear before waiting for any pending frames 892 * This is needed before starting the RF_BUS GRANT sequence other wise causes kernel 893 * panic 894 */ 895 for(i = 0; i < AR9300_ABORT_LOOPS; i++) { 896 if(OS_REG_READ(ah, AR_Q_TXE) == 0) { 897 break; 898 } 899 OS_DELAY(AR9300_ABORT_WAIT); 900 } 901 if (i == AR9300_ABORT_LOOPS) { 902 HALDEBUG(ah, HAL_DEBUG_TX, "%s[%d] reached max wait on TXE\n", 903 __func__, __LINE__); 904 } 905 906 /* 907 * wait on all tx queues 908 * This need to be checked in the last to gain extra 50 usec. on avg. 909 * Currently checked first since we dont have a previous channel information currently. 910 * Which is needed to revert the rf changes. 911 */ 912 for (q = AR_NUM_QCU - 1; q >= 0; q--) { 913 for (i = 0; i < AR9300_ABORT_LOOPS; i++) { 914 if (!(ar9300_num_tx_pending(ah, q))) { 915 break; 916 } 917 OS_DELAY(AR9300_ABORT_WAIT); 918 } 919 if (i == AR9300_ABORT_LOOPS) { 920 status = AH_FALSE; 921 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 922 "ABORT LOOP finsihsed for Q: %d, num_pending: %d \n", 923 q, ar9300_num_tx_pending(ah, q)); 924 goto exit; 925 } 926 } 927 928 /* Updating the beacon alert register with correct value */ 929 OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, nextdba); 930 OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, nexttbtt); 931 932exit: 933 /* 934 * clear tx abort bits 935 */ 936 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); 937 /* Added a new receipe from K31 code */ 938 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH | AR_DIAG_RX_DIS | 939 AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR); 940 OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); 941 942 /* 943 * clear txd 944 */ 945 OS_REG_WRITE(ah, AR_Q_TXD, 0); 946 947 ahp->ah_abort_txdma_norx = AH_TRUE; 948 949 return status; 950} 951 952/* 953 * Determine which tx queues need interrupt servicing. 954 */ 955void 956ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *txqs) 957{ 958 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, 959 "ar9300_get_tx_intr_queue: Should not be called\n"); 960#if 0 961 struct ath_hal_9300 *ahp = AH9300(ah); 962 *txqs &= ahp->ah_intr_txqs; 963 ahp->ah_intr_txqs &= ~(*txqs); 964#endif 965} 966 967void 968ar9300_reset_tx_status_ring(struct ath_hal *ah) 969{ 970 struct ath_hal_9300 *ahp = AH9300(ah); 971 972 ahp->ts_tail = 0; 973 974 /* Zero out the status descriptors */ 975 OS_MEMZERO((void *)ahp->ts_ring, ahp->ts_size * sizeof(struct ar9300_txs)); 976 HALDEBUG(ah, HAL_DEBUG_QUEUE, 977 "%s: TS Start 0x%x End 0x%x Virt %p, Size %d\n", __func__, 978 ahp->ts_paddr_start, ahp->ts_paddr_end, ahp->ts_ring, ahp->ts_size); 979 980 OS_REG_WRITE(ah, AR_Q_STATUS_RING_START, ahp->ts_paddr_start); 981 OS_REG_WRITE(ah, AR_Q_STATUS_RING_END, ahp->ts_paddr_end); 982} 983 984void 985ar9300_setup_tx_status_ring(struct ath_hal *ah, void *ts_start, 986 u_int32_t ts_paddr_start, u_int16_t size) 987{ 988 struct ath_hal_9300 *ahp = AH9300(ah); 989 990 ahp->ts_paddr_start = ts_paddr_start; 991 ahp->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9300_txs)); 992 ahp->ts_size = size; 993 ahp->ts_ring = (struct ar9300_txs *)ts_start; 994 995 ar9300_reset_tx_status_ring(ah); 996} 997