Searched refs:MODE (Results 1 - 25 of 29) sorted by last modified time

12

/u-boot/drivers/serial/
H A Dserial_sti_asc.c22 #define MODE 0x00000001 macro
54 * MODE 0
59 * MODE 1
/u-boot/drivers/power/regulator/
H A Ds2mps11_regulator.c17 #define MODE(_id, _val, _name) { \ macro
25 MODE(OP_OFF, S2MPS11_BUCK_MODE_OFF, "OFF"),
26 MODE(OP_STANDBY, S2MPS11_BUCK_MODE_STANDBY, "ON/OFF"),
27 MODE(OP_ON, S2MPS11_BUCK_MODE_STANDBY, "ON"),
31 MODE(OP_OFF, S2MPS11_LDO_MODE_OFF, "OFF"),
32 MODE(OP_STANDBY, S2MPS11_LDO_MODE_STANDBY, "ON/OFF"),
33 MODE(OP_STANDBY_LPM, S2MPS11_LDO_MODE_STANDBY_LPM, "ON/LPM"),
34 MODE(OP_ON, S2MPS11_LDO_MODE_ON, "ON"),
H A Dsandbox.c16 #define MODE(_id, _val, _name) [_id] = { \ macro
55 MODE(BUCK_OM_OFF, OM2REG(BUCK_OM_OFF), "OFF"),
56 MODE(BUCK_OM_ON, OM2REG(BUCK_OM_ON), "ON"),
57 MODE(BUCK_OM_PWM, OM2REG(BUCK_OM_PWM), "PWM"),
73 MODE(LDO_OM_OFF, OM2REG(LDO_OM_OFF), "OFF"),
74 MODE(LDO_OM_ON, OM2REG(LDO_OM_ON), "ON"),
75 MODE(LDO_OM_SLEEP, OM2REG(LDO_OM_SLEEP), "SLEEP"),
76 MODE(LDO_OM_STANDBY, OM2REG(LDO_OM_STANDBY), "STANDBY"),
H A Dpfuze100.c212 #define MODE(_id, _val, _name) { \ macro
220 MODE(OFF_OFF, OFF_OFF, "OFF_OFF"),
221 MODE(PWM_OFF, PWM_OFF, "PWM_OFF"),
222 MODE(PFM_OFF, PFM_OFF, "PFM_OFF"),
223 MODE(APS_OFF, APS_OFF, "APS_OFF"),
224 MODE(PWM_PWM, PWM_PWM, "PWM_PWM"),
225 MODE(PWM_APS, PWM_APS, "PWM_APS"),
226 MODE(APS_APS, APS_APS, "APS_APS"),
227 MODE(APS_PFM, APS_PFM, "APS_PFM"),
228 MODE(PWM_PF
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H A Dmax77686.c18 #define MODE(_id, _val, _name) { \ macro
26 MODE(OPMODE_OFF, MAX77686_LDO_MODE_OFF, "OFF"),
27 MODE(OPMODE_LPM, MAX77686_LDO_MODE_LPM, "LPM"),
28 MODE(OPMODE_STANDBY_LPM, MAX77686_LDO_MODE_STANDBY_LPM, "ON/LPM"),
29 MODE(OPMODE_ON, MAX77686_LDO_MODE_ON, "ON"),
34 MODE(OPMODE_OFF, MAX77686_LDO_MODE_OFF, "OFF"),
35 MODE(OPMODE_STANDBY, MAX77686_LDO_MODE_STANDBY, "ON/OFF"),
36 MODE(OPMODE_STANDBY_LPM, MAX77686_LDO_MODE_STANDBY_LPM, "ON/LPM"),
37 MODE(OPMODE_ON, MAX77686_LDO_MODE_ON, "ON"),
42 MODE(OPMODE_OF
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/u-boot/board/vscom/baltos/
H A Dboard.c327 {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
332 {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
333 {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
334 {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
335 {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
H A Dmux.c25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
31 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
32 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
33 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
34 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
35 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
36 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
41 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
43 {OFFSET(spi0_cs0), (MODE(
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/u-boot/board/ti/am43xx/
H A Dmux.c15 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
16 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
17 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
18 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
19 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
20 {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
21 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
22 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
23 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
28 {OFFSET(mii1_txen), MODE(
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/u-boot/board/ti/am335x/
H A Dmux.c26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(
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/u-boot/board/tcl/sl50/
H A Dmux.c17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
23 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
24 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
29 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
30 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
35 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
36 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
41 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
42 {OFFSET(gpmc_wpn), (MODE(
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/u-boot/board/phytec/phycore_am335x_r2/
H A Dmux.c17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
24 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
25 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
26 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
27 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
28 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
29 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
30 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
36 {OFFSET(i2c0_sda), (MODE(
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/u-boot/board/isee/igep003x/
H A Dmux.c23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
29 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
30 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
31 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
32 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
33 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
34 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
35 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
40 {OFFSET(gpmc_ad0), (MODE(
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/u-boot/board/grinn/chiliboard/
H A Dboard.c35 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
36 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
41 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
42 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
43 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
44 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
45 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
46 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
51 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
52 {OFFSET(mii1_rxerr), MODE(
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/u-boot/board/eets/pdu001/
H A Dmux.c19 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
20 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
25 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
26 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
31 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
32 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
37 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
38 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
43 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
44 {OFFSET(gpmc_wpn), (MODE(
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/u-boot/board/compulab/cm_t43/
H A Dmux.c12 {OFFSET(mii1_txen), MODE(2)},
13 {OFFSET(mii1_txd3), MODE(2)},
14 {OFFSET(mii1_txd2), MODE(2)},
15 {OFFSET(mii1_txd1), MODE(2)},
16 {OFFSET(mii1_txd0), MODE(2)},
17 {OFFSET(mii1_txclk), MODE(2)},
18 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN},
19 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
20 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN},
21 {OFFSET(mii1_rxd2), MODE(
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/u-boot/board/bosch/shc/
H A Dmux.c22 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */
23 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
24 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */
25 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */
30 {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */
31 {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */
32 {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */
33 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(
[all...]
/u-boot/board/bosch/guardian/
H A Dmux.c18 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
19 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
24 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
25 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
30 {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
31 {OFFSET(mii1_txen), (MODE(7) | PULLDOWN_EN)},
32 {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
33 {OFFSET(mdio_clk), (MODE(7) | PULLUP_EN)},
34 {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
35 {OFFSET(uart1_txd), (MODE(
[all...]
/u-boot/board/BuR/brxre1/
H A Dmux.c20 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
22 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
24 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
26 {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
28 {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
34 {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
36 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
42 {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
44 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
50 {OFFSET(ecap0_in_pwm0_out), (MODE(
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/u-boot/board/BuR/brsmarc1/
H A Dmux.c21 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
23 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
25 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
27 {OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
29 {OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
35 {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
37 {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
39 {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
41 {OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
43 {OFFSET(xdma_event_intr0), MODE(
[all...]
/u-boot/board/BuR/brppt1/
H A Dmux.c20 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
22 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
24 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
32 {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
34 {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
36 {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
38 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
43 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
44 {OFFSET(gpmc_ad6), (MODE(
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/u-boot/arch/arm/mach-omap2/am33xx/
H A Dchilisom.c30 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
32 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
38 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
39 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
40 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
41 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
42 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
43 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
44 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
45 {OFFSET(gpmc_ad7), (MODE(
[all...]
/u-boot/board/siemens/rut/
H A Dmux.c20 {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
21 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
26 {OFFSET(ddr_resetn), (MODE(0))},
27 {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
28 {OFFSET(ddr_ck), (MODE(0))},
29 {OFFSET(ddr_nck), (MODE(0))},
30 {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
31 {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
32 {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
33 {OFFSET(ddr_ba0), (MODE(
[all...]
/u-boot/board/siemens/pxm2/
H A Dmux.c21 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
22 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
23 {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
29 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
30 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
31 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
32 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
33 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
34 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
35 {OFFSET(gpmc_ad6), (MODE(
[all...]
/u-boot/board/siemens/draco/
H A Dmux.c20 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
21 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
26 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
27 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
32 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
34 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
40 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
41 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
42 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
43 {OFFSET(gpmc_ad3), (MODE(
[all...]
/u-boot/board/ti/ks2_evm/
H A Dmux-k2g.h17 { 115, MODE(0) }, /* SOC_UART0_RXD */
18 { 116, MODE(0) }, /* SOC_UART0_TXD */
21 { 223, MODE(0) }, /* SOC_I2C0_SCL */
22 { 224, MODE(0) }, /* SOC_I2C0_SDA */
25 { 225, MODE(0) }, /* SOC_I2C1_SCL */
26 { 226, MODE(0) }, /* SOC_I2C1_SDA */
32 { 0, MODE(0) }, /* GPMCAD0 */
33 { 1, MODE(0) }, /* GPMCAD1 */
34 { 2, MODE(0) }, /* GPMCAD2 */
35 { 3, MODE(
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