| /u-boot/include/ |
| H A D | spd.h | 52 unsigned char twtr; /* 37 Int write to read delay tWTR */ member in struct:spd_eeprom_s
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| H A D | ddr_spd.h | 116 unsigned char twtr; /* 37 Int write to read delay tWTR */ member in struct:ddr2_spd_eeprom_s
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| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | h6_lpddr3.c | 34 u8 twtr = max(ns_to_t(8), 2); local
79 u8 twr2rd = tcwl + 4 + 1 + twtr;
118 writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
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| H A D | h6_ddr3_1333.c | 55 u8 twtr = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */ local
88 u8 twr2rd = tcwl + 2 + twtr; /* (WL + BL / 2 + tWTR) / 2 */
130 writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
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| H A D | lpddr3_stock.c | 16 u8 twtr = max(ns_to_t(8), 2); local
44 u8 twr2rd = tcwl + 4 + 1 + twtr;
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| H A D | ddr2_v3s.c | 16 u8 twtr = max(ns_to_t(8), 2); local
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
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| H A D | ddr3_1333.c | 16 u8 twtr = max(ns_to_t(8), 4); local
44 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
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| /u-boot/arch/arm/include/asm/arch-vf610/ |
| H A D | ddrmc-vf610.h | 27 u8 twtr; member in struct:ddr3_jedec_timings
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3288.h | 56 u32 twtr; member in struct:rk3288_sdram_pctl_timing
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| H A D | sdram_rk3036.h | 57 u32 twtr; member in struct:rk3036_ddr_pctl
254 u32 twtr; member in struct:rk3036_pctl_timing
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| H A D | sdram_rk322x.h | 90 u32 twtr; member in struct:rk322x_ddr_pctl
216 u32 twtr; member in struct:rk322x_pctl_timing
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| H A D | ddr_rk3368.h | 67 u32 twtr; member in struct:rk3368_ddr_pctl
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| H A D | ddr_rk3288.h | 58 u32 twtr; member in struct:rk3288_ddr_pctl
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| /u-boot/drivers/ram/sunxi/ |
| H A D | dram_sun20i_d1.c | 165 u8 twtr; local
211 twtr = ns_to_t(8);
239 twr2rd = twtr + 5;
256 twtr = ns_to_t(8) + 2; // + 2 ? XXX
291 twtp = tcwl + 2 + twtr; // WL+BL/2+tWTR
294 twr2rd = tcwl + twtr; // WL+tWTR
324 twtr = 2;
326 twtr = txp;
354 twr2rd = twtr + 5;
365 twtr
[all...] |
| /u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 99 u8 twtr = max(ns_to_t(8), 4); local
128 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
151 twtr = max(ns_to_t(8), 2);
167 twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */
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| H A D | dram_sun8i_a33.c | 99 u8 twtr = max(ns_to_t(8), 4); local
128 u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
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| H A D | dram_sun6i.c | 222 writel(MCTL_TWTR, &mctl_ctl->twtr);
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| /u-boot/board/phytec/pcm052/ |
| H A D | pcm052.c | 107 .twtr = 4,
162 .twtr = 4,
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| /u-boot/arch/arm/include/asm/arch-omap3/ |
| H A D | mem.h | 82 #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \
83 ACTIM_CTRLB_TWTR(twtr) | \
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| /u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 1054 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; local
1121 twtr = DIV_ROUND_UP(7500, clkper) - 1;
1147 debug("twtr=%d\n", twtr);
1197 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
1287 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; local
1394 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
1396 trtp = twtr;
1426 debug("twtr=%d\n", twtr);
[all...] |
| /u-boot/drivers/ddr/fsl/ |
| H A D | ddr2_dimm_params.c | 312 pdimm->twtr_ps = spd->twtr * 250;
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| /u-boot/arch/arm/mach-imx/ |
| H A D | ddrmc-vf610.c | 133 DDRMC_CR14_TWTR(timings->twtr) |
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| /u-boot/board/toradex/colibri_vf/ |
| H A D | colibri_vf.c | 101 .twtr = 4,
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun6i.h | 90 u32 twtr; /* 0x108 */ member in struct:sunxi_mctl_ctl_reg
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| /u-boot/board/freescale/vf610twr/ |
| H A D | vf610twr.c | 101 .twtr = 4,
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