1/* 2 * sun50i H6 DDR3-1333 timings, as programmed by Allwinner's boot0 3 * for some TV boxes with the H6 and DDR3 memory. 4 * 5 * The chips are probably able to be driven by a faster clock, but boot0 6 * uses a more conservative timing (as usual). 7 * 8 * (C) Copyright 2018,2019 Arm Ltd. 9 * based on previous work by: 10 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 11 * 12 * References used: 13 * - JEDEC DDR3 SDRAM standard: JESD79-3F.pdf 14 * - Samsung K4B2G0446D datasheet 15 * - ZynqMP UG1087 register DDRC/PHY documentation 16 * 17 * Many thanks to Jernej Skrabec for contributing some fixes! 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22#include <common.h> 23#include <asm/arch/dram.h> 24#include <asm/arch/cpu.h> 25 26/* 27 * Only the first four are used for DDR3(?) 28 * MR0: BL8, seq. read burst, no test, fast exit (DLL on), no DLL reset, 29 * CAS latency (CL): 11, write recovery (WR): 12 30 * MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2, 31 * write levelling disabled, TDQS disabled, output buffer enabled 32 * MR2: manual full array self refresh, dynamic ODT off, 33 * CAS write latency (CWL): 8 34 */ 35static u32 mr_ddr3[7] = { 36 0x00001c70, 0x00000040, 0x00000018, 0x00000000, 37 0x00000000, 0x00000400, 0x00000848, 38}; 39 40/* TODO: flexible timing */ 41void mctl_set_timing_params(struct dram_para *para) 42{ 43 struct sunxi_mctl_ctl_reg * const mctl_ctl = 44 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; 45 struct sunxi_mctl_phy_reg * const mctl_phy = 46 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; 47 int i; 48 49 u8 tccd = 2; /* JEDEC: 4nCK */ 50 u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */ 51 u8 trrd = max(ns_to_t(6), 4); /* JEDEC: max(6 ns, 4nCK) */ 52 u8 trcd = ns_to_t(15); /* JEDEC: 13.5 ns */ 53 u8 trc = ns_to_t(53); /* JEDEC: 49.5 ns */ 54 u8 txp = max(ns_to_t(6), 3); /* JEDEC: max(6 ns, 3nCK) */ 55 u8 twtr = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */ 56 u8 trtp = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */ 57 u8 twr = ns_to_t(15); /* JEDEC: 15 ns */ 58 u8 trp = ns_to_t(15); /* JEDEC: >= 13.75 ns */ 59 u8 tras = ns_to_t(38); /* JEDEC >= 36 ns, <= 9*trefi */ 60 u8 twtr_sa = 2; /* ? */ 61 u8 tcksrea = 4; /* ? */ 62 u16 trefi = ns_to_t(7800) / 32; /* JEDEC: 7.8us@Tcase <= 85C */ 63 u16 trfc = ns_to_t(350); /* JEDEC: 160 ns for 2Gb */ 64 u16 txsr = 4; /* ? */ 65 66 u8 tmrw = 0; /* ? */ 67 u8 tmrd = 4; /* JEDEC: 4nCK */ 68 u8 tmod = max(ns_to_t(15), 12); /* JEDEC: max(15 ns, 12nCK) */ 69 u8 tcke = max(ns_to_t(6), 3); /* JEDEC: max(5.625 ns, 3nCK) */ 70 u8 tcksrx = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */ 71 u8 tcksre = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */ 72 u8 tckesr = tcke + 1; /* JEDEC: tCKE(min) + 1nCK */ 73 u8 trasmax = 24; /* JEDEC: tREFI * 9 */ 74 u8 txs = ns_to_t(360) / 32; /* JEDEC: max(5nCK,tRFC+10ns) */ 75 u8 txsdll = 4; /* JEDEC: 512 nCK */ 76 u8 txsabort = 4; /* ? */ 77 u8 txsfast = 4; /* ? */ 78 u8 tcl = 6; /* JEDEC: CL / 2 => 6 */ 79 u8 tcwl = 4; /* JEDEC: 8 */ 80 u8 t_rdata_en = 7; /* ? */ 81 82 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ 83 u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; 84 u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; 85 u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ 86 87 u8 twtp = tcwl + 2 + twr; /* (WL + BL / 2 + tWR) / 2 */ 88 u8 twr2rd = tcwl + 2 + twtr; /* (WL + BL / 2 + tWTR) / 2 */ 89 u8 trd2wr = 5; /* (RL + BL / 2 + 2 - WL) / 2 */ 90 91 if (tcl + 1 >= trtp + trp) 92 trtp = tcl + 2 - trp; 93 94 /* set mode registers */ 95 for (i = 0; i < ARRAY_SIZE(mr_ddr3); i++) 96 writel(mr_ddr3[i], &mctl_phy->mr[i]); 97 98 /* set DRAM timing */ 99 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, 100 &mctl_ctl->dramtmg[0]); 101 writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); 102 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, 103 &mctl_ctl->dramtmg[2]); 104 writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); 105 writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp, 106 &mctl_ctl->dramtmg[4]); 107 writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke, 108 &mctl_ctl->dramtmg[5]); 109 /* Value suggested by ZynqMP manual and used by libdram */ 110 writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); 111 writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs, 112 &mctl_ctl->dramtmg[8]); 113 writel(txsr, &mctl_ctl->dramtmg[14]); 114 115 clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30)); 116 writel(0, &mctl_ctl->dfimisc); 117 clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660); 118 119 /* 120 * Set timing registers of the PHY. 121 * Note: the PHY is clocked 2x from the DRAM frequency. 122 */ 123 writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), 124 &mctl_phy->dtpr[0]); 125 writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); 126 writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]); 127 writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8), 128 &mctl_phy->dtpr[3]); 129 writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]); 130 writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]); 131 writel(0x0505, &mctl_phy->dtpr[6]); 132 133 /* Configure DFI timing */ 134 writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, 135 &mctl_ctl->dfitmg0); 136 writel(0x040201, &mctl_ctl->dfitmg1); 137 138 /* Configure PHY timing. Zynq uses different registers. */ 139 writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]); 140 writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]); 141 142 /* set refresh timing */ 143 writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg); 144} 145