Searched refs:sync (Results 1 - 25 of 93) sorted by relevance

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/u-boot/drivers/video/nexell/
H A Ds5pxx18_dp_hdmi.c121 struct dp_sync_info *sync,
126 sync->h_active_len = 1280;
127 sync->h_sync_width = 40;
128 sync->h_back_porch = 220;
129 sync->h_front_porch = 110;
130 sync->h_sync_invert = 0;
131 sync->v_active_len = 720;
132 sync->v_sync_width = 5;
133 sync->v_back_porch = 20;
134 sync
120 hdmi_get_vsync(int preset, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl) argument
206 hdmi_vsync(struct dp_sync_info *sync) argument
227 hdmi_prepare(struct dp_sync_info *sync) argument
410 hdmi_enable(int input, int preset, struct dp_sync_info *sync, int enable) argument
422 hdmi_setup(int input, int preset, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl) argument
492 nx_hdmi_display(int module, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, struct dp_plane_top *top, struct dp_plane_info *planes, struct dp_hdmi_dev *dev) argument
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H A Ds5pxx18_dp.c50 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl)
68 if (NULL == sync || NULL == ctrl) {
69 debug("error, dp.%d not set sync or pad clock info !!!\n",
76 interlace = sync->interlace;
141 nx_dpc_set_hsync(module, sync->h_active_len, sync->h_sync_width,
142 sync->h_front_porch, sync->h_back_porch,
143 sync->h_sync_invert);
144 nx_dpc_set_vsync(module, sync
49 dp_control_setup(int module, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl) argument
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H A Ds5pxx18_dp_rgb.c16 static int rgb_switch(int module, int input, struct dp_sync_info *sync, argument
39 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
65 rgb_switch(module, input, sync, dev);
67 dp_control_setup(module, sync, ctrl);
38 nx_rgb_display(int module, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, struct dp_plane_top *top, struct dp_plane_info *planes, struct dp_rgb_dev *dev) argument
H A Ds5pxx18_dp_mipi.c205 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
260 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
266 int width = sync->h_active_len;
267 int height = sync->v_active_len;
268 int HFP = sync->h_front_porch;
269 int HBP = sync->h_back_porch;
270 int HS = sync->h_sync_width;
271 int VFP = sync->v_front_porch;
272 int VBP = sync->v_back_porch;
273 int VS = sync
204 mipi_prepare(int module, int input, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, struct dp_mipi_dev *mipi) argument
259 mipi_enable(int module, int input, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, struct dp_mipi_dev *mipi) argument
625 nx_mipi_display(int module, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl, struct dp_plane_top *top, struct dp_plane_info *planes, struct dp_mipi_dev *dev) argument
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/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dcache.c20 sync();
27 sync();
45 sync();
/u-boot/common/
H A Dmemsize.c27 # include <asm/io.h> /* for sync() */
29 # define sync() /* nothing */ macro
59 sync();
61 sync();
68 sync();
70 sync();
73 sync();
79 sync();
83 sync();
/u-boot/arch/powerpc/lib/
H A Dppccache.S57 sync
79 sync /* wait for dcbst's to get to ram */
100 sync
104 sync /* wait for dcbi's to get to ram */
/u-boot/arch/arm/mach-nexell/include/mach/
H A Ddisplay_dev.h14 struct dp_sync_info sync; member in struct:nx_display_dev
H A Ddisplay.h62 /* display sync info for DPC */
97 /* extern sync delay */
103 /* sync offset */
217 struct dp_sync_info sync; member in struct:nx_display_plat
227 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
233 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
238 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
244 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
253 int dp_control_setup(int module, struct dp_sync_info *sync,
/u-boot/post/cpu/mpc83xx/
H A Decc.c82 sync();
93 sync();
98 sync();
102 sync();
107 sync();
132 sync();
/u-boot/arch/powerpc/cpu/mpc83xx/
H A Decc.c194 sync();
252 sync();
285 sync();
290 sync();
294 sync();
299 sync();
304 sync();
324 sync();
329 sync();
335 sync();
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/u-boot/drivers/video/
H A Dnexell_display.c43 static void nx_display_parse_dp_sync(ofnode node, struct dp_sync_info *sync) argument
45 sync->h_active_len = ofnode_read_s32_default(node, "h_active_len", 0);
46 sync->h_sync_width = ofnode_read_s32_default(node, "h_sync_width", 0);
47 sync->h_back_porch = ofnode_read_s32_default(node, "h_back_porch", 0);
48 sync->h_front_porch = ofnode_read_s32_default(node, "h_front_porch", 0);
49 sync->h_sync_invert = ofnode_read_s32_default(node, "h_sync_invert", 0);
50 sync->v_active_len = ofnode_read_s32_default(node, "v_active_len", 0);
51 sync->v_sync_width = ofnode_read_s32_default(node, "v_sync_width", 0);
52 sync->v_back_porch = ofnode_read_s32_default(node, "v_back_porch", 0);
53 sync
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H A Dvideomodes.c43 le left_marging time from sync to picture in pixelclocks
44 ri right_marging time from picture to sync in pixelclocks
45 up upper_margin time from sync to picture
47 hs hsync_len length of horizontal sync
48 vs vsync_len length of vertical sync
49 sync see FB_SYNC_*
146 * le:56,ri:48,up:26,lo:5,hs:152,vs:2,sync:0,vmode:0,accel:0
209 GET_OPTION ("sync:", pPar->sync)
434 mode->sync
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H A Dvideomodes.h10 #define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
11 #define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
12 #define FB_SYNC_EXT 4 /* external sync */
13 #define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
17 #define FB_SYNC_ON_GREEN 32 /* sync on green */
38 int left_margin; /* time from sync to picture */
39 int right_margin; /* time from picture to sync */
40 int upper_margin; /* time from sync to picture */
42 int hsync_len; /* length of horizontal sync */
43 int vsync_len; /* length of vertical sync */
44 int sync; /* see FB_SYNC_* */ member in struct:ctfb_res_modes
[all...]
/u-boot/board/beckhoff/mx53cx9020/
H A Dmx53cx9020_video.c35 .sync = 0,
/u-boot/board/friendlyarm/nanopi2/
H A Dboard.c132 struct dp_sync_info *sync = &dp->sync; local
138 sync->h_active_len = lcd->width;
139 sync->h_sync_width = timing->h_sw;
140 sync->h_back_porch = timing->h_bp;
141 sync->h_front_porch = timing->h_fp;
142 sync->h_sync_invert = !lcd->polarity.inv_hsync;
144 sync->v_active_len = lcd->height;
145 sync->v_sync_width = timing->v_sw;
146 sync
[all...]
/u-boot/board/gdsys/mpc8308/
H A Dsdram.c63 sync();
67 sync();
/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dstart.S238 sync
251 sync
656 sync
682 * CCSRBARL registers, respectively. Follow this with a sync
694 sync /* Make sure we write to CCSRBARH first */
696 sync
700 * Follow this with a sync instruction.
703 sync
709 sync
712 sync
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/u-boot/arch/mips/lib/
H A Dcache.c139 sync();
160 sync();
178 sync();
/u-boot/tools/
H A Dimx8m_image.sh30 dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync
40 dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync
47 dd if=spl/u-boot-spl.bin of=spl/u-boot-spl-pad.bin bs=4 conv=sync
/u-boot/arch/powerpc/cpu/mpc8xxx/
H A Dfsl_pamu.c136 sync();
139 sync();
284 sync();
299 sync();
323 sync();
336 sync();
/u-boot/arch/mips/mach-octeon/
H A Dlowlevel_init.S83 sync
122 sync
/u-boot/drivers/net/qe/
H A Ddm_qe_uec_phy.c41 sync();
78 sync();
/u-boot/arch/mips/mach-mtmips/
H A Dddr_init.c37 sync();
39 sync();
47 sync();
49 sync();
/u-boot/board/ge/mx53ppd/
H A Dmx53ppd_video.c88 .sync = FB_SYNC_EXT,

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