/u-boot/arch/mips/mach-octeon/ |
H A D | cache.c | 11 void flush_dcache_range(ulong start_addr, ulong stop) argument 17 void flush_cache(ulong start_addr, ulong size) argument 21 void invalidate_dcache_range(ulong start_addr, ulong stop) argument
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/u-boot/arch/xtensa/lib/ |
H A D | cache.c | 30 void flush_cache(ulong start_addr, ulong size) argument 32 __flush_invalidate_dcache_range(start_addr, size); 33 __invalidate_icache_range(start_addr, size); 42 void flush_dcache_range(ulong start_addr, ulong end_addr) argument 44 __flush_invalidate_dcache_range(start_addr, end_addr - start_addr);
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/u-boot/cmd/ |
H A D | strings.c | 13 static char *start_addr, *last_addr; variable 21 start_addr = (char *)hextoul(argv[1], NULL); 28 char *addr = start_addr; 35 last_addr = addr + (last_addr - start_addr); 36 start_addr = addr;
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/u-boot/arch/powerpc/cpu/mpc8xxx/ |
H A D | pamu_table.c | 18 tbl->start_addr[i] = 21 tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; 25 tbl->start_addr[i] = 28 tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; 33 tbl->start_addr[i] = 36 tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; 42 debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]);
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/u-boot/arch/mips/lib/ |
H A D | cache.c | 111 void __weak flush_cache(ulong start_addr, ulong size) argument 123 cache_loop(start_addr, start_addr + size, ilsize, 129 cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D); 132 cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD); 135 cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I); 145 void __weak flush_dcache_range(ulong start_addr, ulon argument 163 invalidate_dcache_range(ulong start_addr, ulong stop) argument [all...] |
/u-boot/arch/powerpc/lib/ |
H A D | cache.c | 22 void flush_cache(ulong start_addr, ulong size) argument 27 start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); 28 end = start_addr + size - 1;
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/u-boot/arch/arm/include/asm/ |
H A D | omap_sec_common.h | 37 int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
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H A D | armv7_mpu.h | 86 uint32_t start_addr; member in struct:mpu_region_config
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/u-boot/board/freescale/common/ |
H A D | mpc85xx_sleep.c | 81 u32 start_addr; local 91 start_addr = in_be32(&scfg->sparecr[1]); 92 debug("Entry address is 0x%08x\n", start_addr); 93 kernel_resume = (void (*)(void))start_addr;
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H A D | arm_sleep.c | 114 u32 start_addr; local 124 start_addr = in_le32(&scfg->sparecr[3]); 125 debug("Entry address is 0x%08x\n", start_addr); 126 kernel_resume = (void (*)(void))start_addr;
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/u-boot/cmd/ti/ |
H A D | ddr3.c | 237 u32 start_addr, end_addr, range, ecc_ctrl; local 249 start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) 253 if ((addr >= start_addr) && (addr <= end_addr)) 261 start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) 265 if ((addr >= start_addr) && (addr <= end_addr)) 285 u32 start_addr, end_addr, size, ecc_err; local 293 start_addr = hextoul(argv[2], NULL); 296 if (!is_addr_valid(start_addr)) { 301 ddr_memory_ecc_err(start_addr, ecc_err); 309 start_addr [all...] |
/u-boot/include/ |
H A D | zynq_bootimg.h | 31 int zynq_validate_partition(u32 start_addr, u32 len, u32 chksum_off);
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/u-boot/arch/arm/mach-rockchip/ |
H A D | sdram.c | 176 phys_addr_t start_addr = ddr_info->bank[i]; local 184 if (start_addr < SZ_2M) { 185 size -= SZ_2M - start_addr; 186 start_addr = SZ_2M; 225 if (start_addr >= rsrv_start && start_addr < rsrv_end) { 226 if (rsrv_end - start_addr > size) { 231 size -= rsrv_end - start_addr; 232 start_addr = rsrv_end; 236 if (start_addr < rsrv_star [all...] |
/u-boot/drivers/mmc/ |
H A D | sdhci-adma.c | 58 struct mmc_data *data, dma_addr_t start_addr) 60 dma_addr_t addr = start_addr; 56 sdhci_prepare_adma_table(struct sdhci_host *host, struct sdhci_adma_desc *table, struct mmc_data *data, dma_addr_t start_addr) argument
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H A D | piton_mmc.c | 48 u32 *buff, *start_addr, *write_src; local 54 start_addr = priv->base_addr + start_block; 60 *buff++ = readl(start_addr++); 63 writel(*write_src++,start_addr++);
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/u-boot/arch/mips/mach-mtmips/mt7621/tpl/ |
H A D | tpl.c | 21 * Assume that data is 4-byte aligned and start_addr/size is 32-byte aligned 23 static void fill_lock_l2cache(uintptr_t dataptr, ulong start_addr, ulong size) argument 26 ulong end_addr = start_addr + size; 37 for (addr = start_addr; addr < end_addr; addr += slsize) {
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/u-boot/lib/acpi/ |
H A D | acpi_writer.c | 72 ulong write_acpi_tables(ulong start_addr) argument 82 log_debug("ACPI: Writing ACPI tables at %lx\n", start_addr); 85 acpi_setup_ctx(ctx, start_addr);
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/u-boot/arch/arm/cpu/armv7m/ |
H A D | mpu.c | 38 writel(reg_config->start_addr | VALID_REGION | reg_config->region_no,
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H A D | cache.c | 139 static int action_cache_range(enum cache_action action, u32 start_addr, argument 157 start_addr &= ~(cline_size - 1); 160 writel(start_addr, action_reg); 162 start_addr += cline_size;
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/u-boot/drivers/ddr/altera/ |
H A D | sdram_soc64.c | 141 phys_addr_t start_addr; local 147 start_addr = bd->bi_dram[0].start; 151 memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); 152 gd->arch.tlb_addr = start_addr + PGTABLE_OFF; 154 start_addr += PGTABLE_SIZE + PGTABLE_OFF; 161 sdram_clear_mem(start_addr, size_init); 163 start_addr += size_init; 171 start_addr = bd->bi_dram[bank].start;
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/u-boot/arch/arm/mach-mvebu/ |
H A D | dram.c | 172 u32 start_addr; local 191 start_addr = 0; 196 start_addr = 0x1000000; 197 size -= start_addr; 200 mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
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/u-boot/board/xilinx/zynq/ |
H A D | bootimg.c | 132 int zynq_validate_partition(u32 start_addr, u32 len, u32 chksum_off) argument 139 md5_wd((u8 *)start_addr, len, &calchecksum[0], 0x10000);
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/u-boot/arch/arm/cpu/armv7/ |
H A D | mpu_v7r.c | 72 asm volatile ("mcr p15, 0, %0, c6, c1, 0" : : "r" (rgn->start_addr));
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/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
H A D | mxs.c | 75 void mx28_fixup_vt(uint32_t start_addr) argument 87 vt[i + 8] = start_addr + (4 * i);
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/u-boot/arch/m68k/lib/ |
H A D | cache.c | 15 void flush_cache(ulong start_addr, ulong size) argument
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