/u-boot/drivers/ram/rockchip/ |
H A D | sdram_px30.c | 198 struct px30_sdram_params *sdram_params) 201 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHz * 2); 209 static unsigned int calculate_ddrconfig(struct px30_sdram_params *sdram_params) argument 211 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 221 if (sdram_params->base.dramtype == DDR4) { 243 * argument sdram_params->ch.ddrconf must be right value before 247 struct px30_sdram_params *sdram_params) 249 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 254 if (sdram_params->base.dramtype == DDR4) 271 if (sdram_params 197 rkclk_configure_ddr(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument 246 set_ctl_address_map(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument 416 dram_all_config(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument 432 enable_low_power(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument 484 sdram_init_(struct dram_info *dram, struct px30_sdram_params *sdram_params, u32 pre_init) argument 565 dram_detect_cap(struct dram_info *dram, struct px30_sdram_params *sdram_params, unsigned char channel) argument 646 sdram_init_detect(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument 696 struct px30_sdram_params *sdram_params; local [all...] |
H A D | sdram_rk3288.c | 245 struct rk3288_sdram_params *sdram_params, 250 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; 251 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, 252 sizeof(sdram_params->pctl_timing)); 253 switch (sdram_params->base.dramtype) { 255 writel(sdram_params->pctl_timing.tcl - 1, 257 writel(sdram_params->pctl_timing.tcwl, 268 sdram_params->base.odt); 271 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { 272 writel(sdram_params 244 pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, struct rk3288_sdram_params *sdram_params, struct rk3288_grf *grf) argument 294 phy_cfg(const struct chan_info *chan, int channel, struct rk3288_sdram_params *sdram_params) argument 477 data_training(const struct chan_info *chan, int channel, struct rk3288_sdram_params *sdram_params) argument 580 dram_cfg_rbc(const struct chan_info *chan, u32 chnum, struct rk3288_sdram_params *sdram_params) argument 594 dram_all_config(const struct dram_info *dram, struct rk3288_sdram_params *sdram_params) argument 622 sdram_rank_bw_detect(struct dram_info *dram, int channel, struct rk3288_sdram_params *sdram_params) argument 675 sdram_col_row_detect(struct dram_info *dram, int channel, struct rk3288_sdram_params *sdram_params) argument 729 sdram_get_niu_config(struct rk3288_sdram_params *sdram_params) argument 750 sdram_get_stride(struct rk3288_sdram_params *sdram_params) argument 785 sdram_init(struct dram_info *dram, struct rk3288_sdram_params *sdram_params) argument [all...] |
H A D | sdram_rk3328.c | 45 struct rk3328_sdram_params sdram_params; 120 struct rk3328_sdram_params *sdram_params) 128 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2); 136 static u32 calculate_ddrconfig(struct rk3328_sdram_params *sdram_params) argument 138 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 152 if (sdram_params->base.dramtype == DDR4) { 218 struct rk3328_sdram_params *sdram_params) 220 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 225 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) 227 if (sdram_params 119 rkclk_configure_ddr(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument 217 set_ctl_address_map(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument 304 dram_all_config(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument 320 enable_low_power(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument 342 sdram_init(struct dram_info *dram, struct rk3328_sdram_params *sdram_params, u32 pre_init) argument 398 dram_detect_cap(struct dram_info *dram, struct rk3328_sdram_params *sdram_params, unsigned char channel) argument 471 sdram_init_detect(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument [all...] |
H A D | sdram_rk3188.c | 231 struct rk3188_sdram_params *sdram_params, 234 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, 235 sizeof(sdram_params->pctl_timing)); 236 switch (sdram_params->base.dramtype) { 238 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { 239 writel(sdram_params->pctl_timing.tcl - 3, 242 writel(sdram_params->pctl_timing.tcl - 2, 245 writel(sdram_params->pctl_timing.tcwl - 1, 260 struct rk3188_sdram_params *sdram_params) 264 uint ddr_freq_mhz = sdram_params 230 pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, struct rk3188_sdram_params *sdram_params, struct rk3188_grf *grf) argument 259 phy_cfg(const struct chan_info *chan, int channel, struct rk3188_sdram_params *sdram_params) argument 418 data_training(const struct chan_info *chan, int channel, struct rk3188_sdram_params *sdram_params) argument 522 dram_cfg_rbc(const struct chan_info *chan, u32 chnum, struct rk3188_sdram_params *sdram_params) argument 536 dram_all_config(const struct dram_info *dram, struct rk3188_sdram_params *sdram_params) argument 568 sdram_rank_bw_detect(struct dram_info *dram, int channel, struct rk3188_sdram_params *sdram_params) argument 629 sdram_col_row_detect(struct dram_info *dram, int channel, struct rk3188_sdram_params *sdram_params) argument 684 sdram_get_niu_config(struct rk3188_sdram_params *sdram_params) argument 713 sdram_init(struct dram_info *dram, struct rk3188_sdram_params *sdram_params) argument [all...] |
H A D | sdram_rk3066.c | 219 struct rk3066_dmc_sdram_params *sdram_params, 222 rk3066_dmc_copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, 223 sizeof(sdram_params->pctl_timing)); 224 switch (sdram_params->base.dramtype) { 226 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { 227 writel(sdram_params->pctl_timing.tcl - 3, 230 writel(sdram_params->pctl_timing.tcl - 2, 233 writel(sdram_params->pctl_timing.tcwl - 1, 247 struct rk3066_dmc_sdram_params *sdram_params) 251 uint ddr_freq_mhz = sdram_params 218 rk3066_dmc_pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, struct rk3066_dmc_sdram_params *sdram_params, struct rk3066_grf *grf) argument 246 rk3066_dmc_phy_cfg(const struct rk3066_dmc_chan_info *chan, int channel, struct rk3066_dmc_sdram_params *sdram_params) argument 403 rk3066_dmc_data_training(const struct rk3066_dmc_chan_info *chan, int channel, struct rk3066_dmc_sdram_params *sdram_params) argument 507 rk3066_dmc_dram_cfg_rbc(const struct rk3066_dmc_chan_info *chan, u32 chnum, struct rk3066_dmc_sdram_params *sdram_params) argument 521 rk3066_dmc_dram_all_config(const struct rk3066_dmc_dram_info *dram, struct rk3066_dmc_sdram_params *sdram_params) argument 553 rk3066_dmc_sdram_rank_bw_detect(struct rk3066_dmc_dram_info *dram, int channel, struct rk3066_dmc_sdram_params *sdram_params) argument 606 rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, int channel, struct rk3066_dmc_sdram_params *sdram_params) argument 661 rk3066_dmc_sdram_get_niu_config(struct rk3066_dmc_sdram_params *sdram_params) argument 683 rk3066_dmc_sdram_init(struct rk3066_dmc_dram_info *dram, struct rk3066_dmc_sdram_params *sdram_params) argument [all...] |
H A D | sdram_rk322x.c | 164 struct rk322x_sdram_params *sdram_params) 167 u32 dramtype = sdram_params->base.dramtype; 175 (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) << 180 (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) << 185 (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) << 190 ((sdram_params->phy_timing.mr[0] | 213 (sdram_params->phy_timing.mr[1] & 217 (sdram_params->phy_timing.mr[2] & 221 (sdram_params->phy_timing.mr[3] & 226 (sdram_params 163 memory_init(struct chan_info *chan, struct rk322x_sdram_params *sdram_params) argument 401 pctl_cfg(struct rk322x_ddr_pctl *pctl, struct rk322x_sdram_params *sdram_params, struct rk322x_grf *grf) argument 469 phy_cfg(struct chan_info *chan, struct rk322x_sdram_params *sdram_params) argument 532 dram_cfg_rbc(struct chan_info *chan, struct rk322x_sdram_params *sdram_params) argument 578 dram_all_config(const struct dram_info *dram, struct rk322x_sdram_params *sdram_params) argument 601 dram_cap_detect(struct dram_info *dram, struct rk322x_sdram_params *sdram_params) argument 686 sdram_init(struct dram_info *dram, struct rk322x_sdram_params *sdram_params) argument [all...] |
H A D | sdram_rv1126.c | 366 struct rv1126_sdram_params *sdram_params) 369 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); 373 calculate_ddrconfig(struct rv1126_sdram_params *sdram_params) argument 375 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 391 if (sdram_params->base.dramtype == DDR4) { 462 if (sdram_params->base.dramtype == DDR4) { 500 struct rv1126_sdram_params *sdram_params) 502 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 508 if (sdram_params->base.dramtype == DDR4) { 531 if (sdram_params 365 rkclk_configure_ddr(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 499 set_ctl_address_map(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 850 set_ds_odt(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 dst_fsp) argument 1191 sdram_cmd_dq_path_remap(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 1211 phy_cfg(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 1893 data_training(struct dram_info *dram, u32 cs, struct rv1126_sdram_params *sdram_params, u32 dst_fsp, u32 training_flag) argument 1938 get_wrlvl_val(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2052 high_freq_training(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 fsp) argument 2171 update_noc_timing(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2213 split_setup(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2273 dram_all_config(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2306 enable_low_power(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2337 print_ddr_info(struct rv1126_sdram_params *sdram_params) argument 2352 sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init) argument 2469 dram_detect_cap(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, unsigned char channel) argument 2618 dram_detect_cs1_row(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, unsigned char channel) argument 2687 sdram_init_detect(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2802 pre_set_rate(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 dst_fsp, u32 dst_fsp_lp4) argument 2928 save_fsp_param(struct dram_info *dram, u32 dst_fsp, struct rv1126_sdram_params *sdram_params) argument 3167 ddr_set_rate(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 freq, u32 cur_freq, u32 dst_fsp, u32 dst_fsp_lp4, u32 training_en) argument 3350 ddr_set_rate_for_fsp(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 3423 struct rv1126_sdram_params *sdram_params; local [all...] |
H A D | sdram_rk3399.c | 102 struct rk3399_sdram_params sdram_params; 3031 (u32 *)&plat->sdram_params, 3032 sizeof(plat->sdram_params) / sizeof(u32)); 3081 struct rk3399_sdram_params *params = &plat->sdram_params;
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/u-boot/arch/arm/include/asm/arch-tegra20/ |
H A D | sdram_param.h | 27 struct sdram_params { struct
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/u-boot/arch/arm/mach-tegra/tegra20/ |
H A D | warmboot.c | 121 struct sdram_params sdram; 135 /* get ram code that is used as index to array sdram_params in BCT */ 139 (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
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