ram/rockchip/sdram_rk3288.c

245 		     struct rk3288_sdram_params *sdram_params,
250 	burstlen = (sdram_params->base.noc_timing >> 18) & 0x7;
251 	copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
252 		    sizeof(sdram_params->pctl_timing));
253 	switch (sdram_params->base.dramtype) {
255 		writel(sdram_params->pctl_timing.tcl - 1,
257 		writel(sdram_params->pctl_timing.tcwl,
268 				   sdram_params->base.odt);
271 		if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
272 			writel(sdram_params->pctl_timing.tcl - 3,
275 			writel(sdram_params->pctl_timing.tcl - 2,
278 		writel(sdram_params->pctl_timing.tcwl - 1,
295 		    struct rk3288_sdram_params *sdram_params)
299 	uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
305 	copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
306 		    sizeof(sdram_params->phy_timing));
307 	writel(sdram_params->base.noc_timing, &msch->ddrtiming);
309 	writel(sdram_params->base.noc_activate, &msch->activate);
322 	switch (sdram_params->base.dramtype) {
350 	if (sdram_params->base.odt) {
478 			 struct rk3288_sdram_params *sdram_params)
491 	if (sdram_params->base.dramtype != LPDDR3)
493 	rank = sdram_params->ch[channel].rank | 1;
531 	if (sdram_params->base.dramtype != LPDDR3)
535 	writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
581 			 struct rk3288_sdram_params *sdram_params)
585 	if (sdram_params->ch[chnum].bk == 3)
591 	writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
595 			    struct rk3288_sdram_params *sdram_params)
600 	sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
601 	sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
602 	for (chan = 0; chan < sdram_params->num_channels; chan++) {
604 			&sdram_params->ch[chan];
616 		dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
619 	rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
623 		struct rk3288_sdram_params *sdram_params)
630 	if (data_training(chan, channel, sdram_params) < 0) {
638 			sdram_params->num_channels = 1;
643 			sdram_params->ch[channel].rank = 1;
645 					sdram_params->ch[channel].rank << 18);
650 			sdram_params->ch[channel].bw = 1;
652 					    sdram_params->ch[channel].bw,
658 	sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
661 	    (data_training(chan, channel, sdram_params) < 0)) {
662 		if (sdram_params->base.dramtype == LPDDR3) {
676 		struct rk3288_sdram_params *sdram_params)
689 			(1 << (col + sdram_params->ch[channel].bw - 1));
700 		sdram_params->ch[channel].col = col;
719 		sdram_params->ch[channel].cs1_row = row;
720 		sdram_params->ch[channel].row_3_4 = 0;
722 		sdram_params->ch[channel].cs0_row = row;
729 static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params)
733 	tmp = sdram_params->ch[0].col - 9;
734 	tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
735 	tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4);
744 		sdram_params->base.ddrconfig = i;
750 static int sdram_get_stride(struct rk3288_sdram_params *sdram_params)
754 	long cap = sdram_params->num_channels * (1u <<
755 			(sdram_params->ch[0].cs0_row +
756 			 sdram_params->ch[0].col +
757 			 (sdram_params->ch[0].rank - 1) +
758 			 sdram_params->ch[0].bw +
780 	sdram_params->base.stride = stride;
786 		      struct rk3288_sdram_params *sdram_params)
793 	if ((sdram_params->base.dramtype == DDR3 &&
794 	     sdram_params->base.ddr_freq > 800000000) ||
795 	    (sdram_params->base.dramtype == LPDDR3 &&
796 	     sdram_params->base.ddr_freq > 533000000)) {
802 	ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
820 		phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
822 		dfi_cfg(pctl, sdram_params->base.dramtype);
824 		pctl_cfg(channel, pctl, sdram_params, dram->grf);
826 		phy_cfg(chan, channel, sdram_params);
834 		memory_init(publ, sdram_params->base.dramtype);
837 		if (sdram_params->base.dramtype == LPDDR3) {
845 					sdram_params->phy_timing.mr[1]);
848 					sdram_params->phy_timing.mr[2]);
851 					sdram_params->phy_timing.mr[3]);
856 		sdram_params->ch[channel].bw = 2;
858 				    sdram_params->ch[channel].bw, dram->grf);
865 		sdram_params->ch[channel].rank = 2;
867 				(sdram_params->ch[channel].rank | 1) << 18);
876 		if (sdram_params->base.dramtype == LPDDR3) {
880 					sdram_params->ch[channel].rank | 1,
882 					sdram_params->base.odt ? 3 : 0);
895 		sdram_rank_bw_detect(dram, channel, sdram_params);
897 		if (sdram_params->base.dramtype == LPDDR3) {
906 		sdram_params->ch[channel].bk = 3;
908 		ret = sdram_col_row_detect(dram, channel, sdram_params);
913 	ret = sdram_get_niu_config(sdram_params);
917 	ret = sdram_get_stride(sdram_params);
921 	dram_all_config(dram, sdram_params);