| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 93 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, function
139 rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
140 rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
146 rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
147 rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
310 rkclk_set_pll(cru, DPLL, dpll_cfg);
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| H A D | clk_rk3188.c | 89 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, function
156 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
205 rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
389 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
390 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
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| H A D | clk_rk3036.c | 48 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, function
95 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
96 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk322x.c | 46 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, function
97 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
98 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
347 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
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| H A D | clk_rk3128.c | 41 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, function
156 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
157 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
443 rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
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| H A D | clk_rk3399.c | 325 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) function
440 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
475 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
714 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
888 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
1396 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1397 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1667 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
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| H A D | clk_rk3288.c | 150 static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id, function
214 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
355 rkclk_set_pll(cru, CLK_NEW, &npll_config);
440 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
441 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
507 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
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| H A D | clk_rv1108.c | 70 static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, function
647 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
648 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk3328.c | 214 static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id, function
296 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
297 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
321 rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
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| H A D | clk_px30.c | 205 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode, function
821 rkclk_set_pll(&cru->pll[CPLL], &cru->mode,
846 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL,
1138 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz))
1162 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz))
1179 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz))
1583 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz);
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