Searched refs:reg_mask (Results 1 - 10 of 10) sorted by relevance

/u-boot/drivers/net/
H A Dmdio_mux_i2creg.c52 u32 reg_mask[2]; local
57 err = dev_read_u32_array(dev, "mux-reg-masks", reg_mask, 2);
88 priv->reg = (int)reg_mask[0];
89 priv->mask = (int)reg_mask[1];
H A Dmdio_mux_mmioreg.c83 u32 reg_mask; local
97 err = dev_read_u32(dev, "mux-mask", &reg_mask);
103 if (reg_mask >= BIT(reg_size * 8)) {
110 priv->mask = reg_mask;
112 debug("%s: %llx@%lld / %x\n", __func__, reg_base, reg_size, reg_mask);
/u-boot/drivers/bootcount/
H A Dbootcount_syscon.c30 * @reg_mask: mask used to identify the location of the bootcount value
40 u32 reg_mask; member in struct:bootcount_syscon_priv
60 __func__, regval, priv->reg_mask);
62 return regmap_update_bits(priv->regmap, priv->reg_addr, priv->reg_mask,
76 regval &= priv->reg_mask;
137 priv->reg_mask = GEN_REG_MASK(priv->size, bootcount_offset);
/u-boot/drivers/pinctrl/mvebu/
H A Dpinctrl-armada-37xx.c64 * @reg_mask: Bit mask matching the group in the selection register
74 u32 reg_mask; member in struct:armada_37xx_pin_group
108 .reg_mask = 0, \
118 .reg_mask = _mask, \
128 .reg_mask = _mask, \
138 .reg_mask = _mask, \
149 .reg_mask = _mask, \
281 unsigned int mask = grp->reg_mask;
380 unsigned int mask = grp->reg_mask;
403 unsigned int mask = grp->reg_mask;
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/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_def.h159 unsigned int reg_mask; member in struct:reg_data
H A Dddr3_training_ip_flow.h84 u32 reg_addr, u32 data_value, u32 reg_mask);
H A Dddr3_training_leveling.c1743 u32 reg_val, reg_mask; local
1764 reg_mask = (TRAINING_ECC_MUX_MASK << TRAINING_ECC_MUX_OFFS) |
1766 reg_val &= ~reg_mask;
1773 reg_mask = (TRN_START_MASK << TRN_START_OFFS);
1774 reg_val &= ~reg_mask;
1807 reg_mask = SDRAM_OP_CMD_ALL_CS_MASK << SDRAM_OP_CMD_CS_OFFS(0) |
1810 SDRAM_OP_REG, reg_val, reg_mask);
1827 reg_mask = SDRAM_OP_CMD_ALL_CS_MASK << SDRAM_OP_CMD_CS_OFFS(0) |
1830 SDRAM_OP_REG, reg_val, reg_mask);
2067 reg_mask
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H A Dddr3_init.h156 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
H A Dddr3_training.c1124 u32 data_value, u32 reg_mask)
1142 data_value = (data_val & (~reg_mask)) | (data_value & reg_mask);
2095 odpg_default_value[index_cnt].reg_mask));
1121 ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type, u32 interface_id, u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 data_value, u32 reg_mask) argument
/u-boot/drivers/memory/
H A Dstm32-fmc2-ebi.c204 * @reg_mask: the bit that have to be modified in the selected register
220 u32 reg_mask; member in struct:stm32_fmc2_prop
430 clrsetbits_le32(ebi->io_base + reg, prop->reg_mask,
431 setup ? prop->reg_mask : 0);
842 .reg_mask = FMC2_BCR1_CCLKEN,
850 .reg_mask = FMC2_BCR_MUXEN,
863 .reg_mask = FMC2_BCR_WAITPOL,
870 .reg_mask = FMC2_BCR_WAITCFG,
878 .reg_mask = FMC2_BCR_WAITEN,
886 .reg_mask
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