1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
4 */
5
6#ifndef _DDR3_INIT_H
7#define _DDR3_INIT_H
8
9#include "ddr_ml_wrapper.h"
10#include "mv_ddr_plat.h"
11
12#include "ddr3_logging_def.h"
13#include "ddr3_training_hw_algo.h"
14#include "ddr3_training_ip.h"
15#include "ddr3_training_ip_centralization.h"
16#include "ddr3_training_ip_engine.h"
17#include "ddr3_training_ip_flow.h"
18#include "ddr3_training_ip_pbs.h"
19#include "ddr3_training_ip_prv_if.h"
20#include "ddr3_training_leveling.h"
21#include "xor.h"
22
23/* For checking function return values */
24#define CHECK_STATUS(orig_func)		\
25	{				\
26		int status;		\
27		status = orig_func;	\
28		if (MV_OK != status)	\
29			return status;	\
30	}
31
32#define SUB_VERSION	0
33
34enum log_level  {
35	MV_LOG_LEVEL_0,
36	MV_LOG_LEVEL_1,
37	MV_LOG_LEVEL_2,
38	MV_LOG_LEVEL_3
39};
40
41/* TODO: consider to move to misl phy driver */
42#define MISL_PHY_DRV_P_OFFS	0x7
43#define MISL_PHY_DRV_N_OFFS	0x0
44#define MISL_PHY_ODT_P_OFFS	0x6
45#define MISL_PHY_ODT_N_OFFS	0x0
46
47/* Globals */
48extern u8 debug_training, debug_calibration, debug_ddr4_centralization,
49	debug_tap_tuning, debug_dm_tuning;
50extern u8 is_reg_dump;
51extern u8 generic_init_controller;
52/* list of allowed frequency listed in order of enum mv_ddr_freq */
53extern u32 is_pll_old;
54extern struct pattern_info pattern_table[];
55extern u8 debug_centralization, debug_training_ip, debug_training_bist,
56	debug_pbs, debug_training_static, debug_leveling;
57extern struct hws_tip_config_func_db config_func_info[];
58extern u8 twr_mask_table[];
59extern u8 cl_mask_table[];
60extern u8 cwl_mask_table[];
61extern u32 speed_bin_table_t_rc[];
62extern u32 speed_bin_table_t_rcd_t_rp[];
63
64extern u32 vref_init_val;
65extern u32 g_zpri_data;
66extern u32 g_znri_data;
67extern u32 g_zpri_ctrl;
68extern u32 g_znri_ctrl;
69extern u32 g_zpodt_data;
70extern u32 g_znodt_data;
71extern u32 g_zpodt_ctrl;
72extern u32 g_znodt_ctrl;
73extern u32 g_dic;
74extern u32 g_odt_config;
75extern u32 g_rtt_nom;
76extern u32 g_rtt_wr;
77extern u32 g_rtt_park;
78
79extern u8 debug_training_access;
80extern u32 first_active_if;
81extern u32 delay_enable, ck_delay, ca_delay;
82extern u32 mask_tune_func;
83extern u32 rl_version;
84extern int rl_mid_freq_wa;
85extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
86extern enum mv_ddr_freq medium_freq;
87
88extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
89extern enum mv_ddr_freq low_freq;
90extern enum auto_tune_stage training_stage;
91extern u32 is_pll_before_init;
92extern u32 is_adll_calib_before_init;
93extern u32 is_dfs_in_init;
94extern int wl_debug_delay;
95extern u32 silicon_delay[MAX_DEVICE_NUM];
96extern u32 start_pattern, end_pattern;
97extern u32 phy_reg0_val;
98extern u32 phy_reg1_val;
99extern u32 phy_reg2_val;
100extern u32 phy_reg3_val;
101extern enum hws_pattern sweep_pattern;
102extern enum hws_pattern pbs_pattern;
103extern u32 g_znri_data;
104extern u32 g_zpri_data;
105extern u32 g_znri_ctrl;
106extern u32 g_zpri_ctrl;
107extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
108	n_finger_end, p_finger_step, n_finger_step;
109extern u32 mode_2t;
110extern u32 xsb_validate_type;
111extern u32 xsb_validation_base_address;
112extern u32 odt_additional;
113extern u32 debug_mode;
114extern u32 debug_dunit;
115extern u32 clamp_tbl[];
116extern u32 freq_mask[MAX_DEVICE_NUM][MV_DDR_FREQ_LAST];
117
118extern u32 maxt_poll_tries;
119extern u32 is_bist_reset_bit;
120
121extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
122extern u32 effective_cs;
123extern int ddr3_tip_centr_skip_min_win_check;
124extern u32 *dq_map_table;
125
126extern u8 debug_training_hw_alg;
127
128extern u32 start_xsb_offset;
129extern u32 odt_config;
130
131extern u16 mask_results_dq_reg_map[];
132
133extern u32 target_freq;
134extern u32 dfs_low_freq;
135
136extern u32 nominal_avs;
137extern u32 extension_avs;
138
139#if defined(CONFIG_DDR4)
140/* if 1, SSTL & POD have same Vref and workaround is required */
141extern u8 vref_calibration_wa;
142#endif /* CONFIG_DDR4 */
143
144/* Prototypes */
145int ddr3_init(void);
146int ddr3_tip_enable_init_sequence(u32 dev_num);
147
148int ddr3_hws_hw_training(enum hws_algo_type algo_mode);
149int mv_ddr_early_init(void);
150int mv_ddr_early_init2(void);
151int ddr3_silicon_post_init(void);
152int ddr3_post_run_alg(void);
153void ddr3_new_tip_ecc_scrub(void);
154
155int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
156int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
157int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
158#if defined(CONFIG_DDR4)
159int mv_ddr4_mode_regs_init(u8 dev_num);
160int mv_ddr4_sdram_config(u32 dev_num);
161int mv_ddr4_phy_config(u32 dev_num);
162int mv_ddr4_calibration_adjust(u32 dev_num, u8 vref_en, u8 pod_only);
163int mv_ddr4_training_main_flow(u32 dev_num);
164#endif /* CONFIG_DDR4 */
165
166int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
167int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
168int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
169		     int reg_addr, u32 mask);
170int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
171			 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
172int ddr3_tip_restore_dunit_regs(u32 dev_num);
173void print_topology(struct mv_ddr_topology_map *tm);
174
175u32 mv_board_id_get(void);
176
177int ddr3_load_topology_map(void);
178void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
179void mv_ddr_user_log_level_set(enum ddr_lib_debug_block block);
180int ddr3_tip_tune_training_params(u32 dev_num,
181				  struct tune_train_params *params);
182void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
183void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
184u32 mv_board_id_index_get(u32 board_id);
185void ddr3_set_log_level(u32 n_log_level);
186
187int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
188
189int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
190int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
191void mv_ddr_mc_config(void);
192int mv_ddr_mc_init(void);
193void mv_ddr_set_calib_controller(void);
194/* TODO: consider to move to misl phy driver */
195unsigned int mv_ddr_misl_phy_drv_data_p_get(void);
196unsigned int mv_ddr_misl_phy_drv_data_n_get(void);
197unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void);
198unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void);
199unsigned int mv_ddr_misl_phy_odt_p_get(void);
200unsigned int mv_ddr_misl_phy_odt_n_get(void);
201#if defined(CONFIG_DDR4)
202void refresh(void);
203#endif
204
205#endif /* _DDR3_INIT_H */
206