1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6#ifndef _DDR3_TRAINING_IP_DEF_H 7#define _DDR3_TRAINING_IP_DEF_H 8 9#define PATTERN_55 0x55555555 10#define PATTERN_AA 0xaaaaaaaa 11#define PATTERN_80 0x80808080 12#define PATTERN_20 0x20202020 13#define PATTERN_01 0x01010101 14#define PATTERN_FF 0xffffffff 15#define PATTERN_00 0x00000000 16 17/* 16bit bus width patterns */ 18#define PATTERN_55AA 0x5555aaaa 19#define PATTERN_00FF 0x0000ffff 20#define PATTERN_0080 0x00008080 21 22#define INVALID_VALUE 0xffffffff 23#define MAX_NUM_OF_DUNITS 32 24/* 25 * length *2 = length in words of pattern, first low address, 26 * second high address 27 */ 28#define TEST_PATTERN_LENGTH 4 29#define KILLER_PATTERN_DQ_NUMBER 8 30#define SSO_DQ_NUMBER 4 31#define PATTERN_MAXIMUM_LENGTH 64 32#define ADLL_TX_LENGTH 64 33#define ADLL_RX_LENGTH 32 34 35#define PARAM_NOT_CARE 0 36#define PARAM_UNDEFINED 0xffffffff 37 38#define READ_LEVELING_PHY_OFFSET 2 39#define WRITE_LEVELING_PHY_OFFSET 0 40 41#define MASK_ALL_BITS 0xffffffff 42 43#define CS_BIT_MASK 0xf 44 45/* DFX access */ 46#define BROADCAST_ID 28 47#define MULTICAST_ID 29 48 49#define XSB_BASE_ADDR 0x00004000 50#define XSB_CTRL_0_REG 0x00000000 51#define XSB_CTRL_1_REG 0x00000004 52#define XSB_CMD_REG 0x00000008 53#define XSB_ADDRESS_REG 0x0000000c 54#define XSB_DATA_REG 0x00000010 55#define PIPE_ENABLE_ADDR 0x000f8000 56#define ENABLE_DDR_TUNING_ADDR 0x000f829c 57 58#define CLIENT_BASE_ADDR 0x00002000 59#define CLIENT_CTRL_REG 0x00000000 60 61#define TARGET_INT 0x1801 62#define TARGET_EXT 0x180e 63#define BYTE_EN 0 64#define CMD_READ 0 65#define CMD_WRITE 1 66 67#define INTERNAL_ACCESS_PORT 1 68#define EXECUTING 1 69#define ACCESS_EXT 1 70#define CS2_EXIST_BIT 2 71#define TRAINING_ID 0xf 72#define EXT_TRAINING_ID 1 73#define EXT_MODE 0x4 74 75#define GET_RESULT_STATE(res) (res) 76#define SET_RESULT_STATE(res, state) (res = state) 77 78#define ADDR_SIZE_512MB 0x04000000 79#define ADDR_SIZE_1GB 0x08000000 80#define ADDR_SIZE_2GB 0x10000000 81#define ADDR_SIZE_4GB 0x20000000 82#define ADDR_SIZE_8GB 0x40000000 83#define ADDR_SIZE_16GB 0x80000000 84 85 86enum hws_edge_compare { 87 EDGE_PF, 88 EDGE_FP, 89 EDGE_FPF, 90 EDGE_PFP 91}; 92 93enum hws_control_element { 94 HWS_CONTROL_ELEMENT_ADLL, /* per bit 1 edge */ 95 HWS_CONTROL_ELEMENT_DQ_SKEW, 96 HWS_CONTROL_ELEMENT_DQS_SKEW 97}; 98 99enum hws_search_dir { 100 HWS_LOW2HIGH, 101 HWS_HIGH2LOW, 102 HWS_SEARCH_DIR_LIMIT 103}; 104 105enum hws_operation { 106 OPERATION_READ = 0, 107 OPERATION_WRITE = 1 108}; 109 110enum hws_training_ip_stat { 111 HWS_TRAINING_IP_STATUS_FAIL, 112 HWS_TRAINING_IP_STATUS_SUCCESS, 113 HWS_TRAINING_IP_STATUS_TIMEOUT 114}; 115 116enum hws_ddr_cs { 117 CS_SINGLE, 118 CS_NON_SINGLE 119}; 120 121enum hws_ddr_phy { 122 DDR_PHY_DATA = 0, 123 DDR_PHY_CONTROL = 1 124}; 125 126enum hws_dir { 127 OPER_WRITE, 128 OPER_READ, 129 OPER_WRITE_AND_READ 130}; 131 132enum hws_wl_supp { 133 PHASE_SHIFT, 134 CLOCK_SHIFT, 135 ALIGN_SHIFT 136}; 137 138enum mv_ddr_tip_bit_state { 139 BIT_LOW_UI, 140 BIT_HIGH_UI, 141 BIT_SPLIT_IN, 142 BIT_SPLIT_OUT, 143 BIT_STATE_LAST 144}; 145 146enum mv_ddr_tip_byte_state{ 147 BYTE_NOT_DEFINED, 148 BYTE_HOMOGENEOUS_LOW = 0x1, 149 BYTE_HOMOGENEOUS_HIGH = 0x2, 150 BYTE_HOMOGENEOUS_SPLIT_IN = 0x4, 151 BYTE_HOMOGENEOUS_SPLIT_OUT = 0x8, 152 BYTE_SPLIT_OUT_MIX = 0x10, 153 BYTE_STATE_LAST 154}; 155 156struct reg_data { 157 unsigned int reg_addr; 158 unsigned int reg_data; 159 unsigned int reg_mask; 160}; 161 162enum dm_direction { 163 DM_DIR_INVERSE, 164 DM_DIR_DIRECT 165}; 166 167#endif /* _DDR3_TRAINING_IP_DEF_H */ 168