Searched refs:rdiv (Results 1 - 4 of 4) sorted by relevance
| /u-boot/drivers/clk/imx/ |
| H A D | clk-fracn-gppll.c | 60 .rdiv = (_rdiv), \
70 .rdiv = (_rdiv), \
83 * Fvco = (Fref / rdiv) * (MFI + MFN / MFD)
85 * The (Fref / rdiv) should be in range 20MHz to 40MHz
106 * Fvco = (Fref / rdiv) * MFI
108 * The (Fref / rdiv) should be in range 20MHz to 40MHz
157 u32 mfi, mfn, mfd, rdiv, odiv; local
171 rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
182 rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv
[all...] |
| H A D | clk.h | 58 unsigned int rdiv; member in struct:imx_fracn_gppll_rate_table
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| /u-boot/arch/arm/include/asm/arch-imx9/ |
| H A D | clock.h | 171 int rdiv; member in struct:imx_intpll_rate_table
178 int rdiv; member in struct:imx_fracpll_rate_table
188 .rdiv = (_r), \
196 .rdiv = (_r), \
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| /u-boot/arch/arm/mach-imx/imx9/ |
| H A D | clock.c | 53 int rdiv, mfi, mfn, mfd; local
67 rdiv = (div & GENMASK(15, 13)) >> 13;
69 if (rdiv == 0)
70 rdiv = 1;
77 clk = clk * (mfi * mfd + mfn) / mfd / rdiv;
79 clk = clk * mfi / rdiv;
220 writel((rate->odiv & GENMASK(7, 0)) | ((rate->rdiv << 13) & GENMASK(15, 13)) |
286 writel((rate->odiv & GENMASK(7, 0)) | ((rate->rdiv << 13) & GENMASK(15, 13)) |
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