/u-boot/arch/sh/lib/ |
H A D | ashiftrt.S | 56 rotcl r4 58 subc r4,r4 60 shar r4 62 shar r4 64 shar r4 66 shar r4 68 shar r4 70 shar r4 72 shlr16 r4 [all...] |
H A D | udivsi3.S | 15 div1 r5,r4 17 div1 r5,r4; div1 r5,r4; div1 r5,r4 18 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4 21 div1 r5,r4; rotcl r0 22 div1 r5,r4; rotc [all...] |
H A D | udivsi3_i4i-Os.S | 28 mov.l r4,@-r15 31 swap.w r4,r0 32 shlr16 r4 38 div1 r5,r4 40 div1 r5,r4 41 div1 r5,r4 43 div1 r5,r4 44 xtrct r4,r0 45 xtrct r0,r4 47 swap.w r4,r [all...] |
H A D | movmem.S | 35 mov.l r0,@(60,r4) 39 mov.l r0,@(56,r4) 43 mov.l r0,@(52,r4) 44 add #64,r4 53 mov.l r0,@(56,r4) 56 mov.l r0,@(52,r4) 64 mov.l r0,@(60,r4) 70 mov.l r0,@(56,r4) 76 mov.l r0,@(52,r4) 82 mov.l r0,@(48,r4) [all...] |
H A D | start.S | 22 mov.l ._reloc_dst, r4 38 mov.l r1, @r4 39 add #4, r4 40 cmp/hs r6, r4 44 mov.l ._bss_start, r4 48 3: mov.l r1, @r4 /* bss clear */ 49 add #4, r4 50 cmp/hs r5, r4 62 mov #0, r4
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H A D | udivsi3_i4i.S | 43 mov r4,r0 53 mov.l r4,@-r15 66 mov.l r4,@-r15 76 dmulu.l r1,r4 79 mov r4,r0 83 addc r4,r0 84 mov.l @r15+,r4 90 neg r4,r0 94 mov.l @r15+,r4 107 mov.l r4, [all...] |
/u-boot/arch/powerpc/lib/ |
H A D | ppccache.S | 70 subf r4,r3,r4 71 add r4,r4,r5 72 srwi. r4,r4,L1_CACHE_SHIFT 74 mtctr r4 94 subf r4,r3,r4 95 add r4,r [all...] |
H A D | ppcstring.S | 13 addi r4,r4,-1 14 1: lbzu r0,1(r4) 26 addi r4,r4,-1 27 1: lbzu r0,1(r4) 36 addi r4,r4,-1 41 1: lbzu r0,1(r4) 50 addi r4,r [all...] |
H A D | _ashrdi3.S | 34 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 39 or r4,r4,r6 # LSW |= t1 42 or r4,r4,r7 # LSW |= t2
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H A D | _lshrdi3.S | 34 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 38 or r4,r4,r6 # LSW |= t1 40 or r4,r4,r7 # LSW |= t2
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H A D | _ashldi3.S | 36 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) 37 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) 39 slw r4,r4,r5 # LSW = LSW << count
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H A D | ticks.S | 21 mftb r4 41 addc r14, r4, r14 /* Compute end time lower */ 48 subfc r4, r4, r14 /* Subtract current time from end time */
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/u-boot/post/lib_powerpc/ |
H A D | asm.S | 26 mr r3, r4 27 mr r4, r5 49 mr r3, r4 50 mr r4, r5 69 stwu r4, -4(r1) 73 mr r4, r6 76 lwz r4, 0(r1) 77 stw r3, 0(r4) 90 stwu r4, -4(r1) 96 lwz r4, [all...] |
/u-boot/arch/arm/mach-s5pc1xx/ |
H A D | reset.S | 16 ldr r4, =0x00010000 17 and r4, r2, r4 18 cmp r4, #0
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/u-boot/arch/powerpc/cpu/mpc83xx/ |
H A D | start.S | 106 mflr r4 111 mtspr SRR0, r4 146 lis r4, CONFIG_DEFAULT_IMMR@h 158 lwz r6, IMMRBAR(r4) 161 stw r3, IMMRBAR(r4) 191 lis r4, (CONFIG_SYS_MONITOR_BASE)@h 192 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l 193 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET 237 /* r4 [all...] |
/u-boot/arch/nios2/cpu/ |
H A D | start.S | 32 ori r4, r0, %lo(ICACHE_LINE_SIZE) 36 sub r5, r5, r4 61 ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN) 66 add r6, r6, r4 75 nextpc r4 78 sub r4, r4, r5 /* r4 <- cur _start */ 79 mov r8, r4 83 beq r4, r [all...] |
/u-boot/arch/arm/mach-omap2/omap5/ |
H A D | sec_entry_cpu1.S | 38 ldr r4, =omap_smc_sec_cpu1_args 39 ldm r4, {r0,r1,r2,r3} @ Retrieve args 61 ldr r4, =omap_smc_sec_cpu1_args 62 str r0, [r4, #0x10] @ save return value 63 ldr r4, =AUX_CORE_BOOT_0 65 str r5, [r4] 66 ldr r4, =ROM_FXN_STARTUP_BOOTSLAVE 68 bx r4 @ Jump back to ROM 79 push {r4, r5, lr} 80 ldr r4, [all...] |
/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 185 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 186 cmpw r3,r4 190 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 191 cmpw r3,r4 204 li r4,0x48 205 rlwimi r3,r4,0,0x1f8 230 and. r4, r3, r2 250 andc r4, r3, r2 253 mtspr SPRN_L2CSR0,r4 347 li r4,CriticalInpu [all...] |
/u-boot/arch/arm/cpu/armv7/ |
H A D | smccc-call.S | 30 push {r4-r7} 31 UNWIND( .save {r4-r7}) 32 ldm r12, {r4-r7} 34 pop {r4-r7}
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/u-boot/arch/arm/include/asm/arch-mx7/ |
H A D | mx7_plugin.S | 14 push {r0-r4, lr} 34 pop {r0-r4, lr} 58 ldr r4, [r3] 60 ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] 61 blx r4 70 pop {r0-r4, lr}
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/u-boot/arch/arm/mach-renesas/ |
H A D | lowlevel_init_ca15.S | 15 mrc p15, 0, r4, c0, c0, 5 /* mpidr */ 16 orr r4, r4, r4, lsr #6 17 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ 47 tst r4, #4
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/u-boot/arch/arm/include/asm/arch-mx6/ |
H A D | mx6_plugin.S | 24 push {r0-r4, lr} 47 ldr r4, [r3] 48 cmp r4, #ROM_VERSION_TO10 51 ldr r4, =0x50000000 52 str r4, [r3, #0x5c] 55 ldr r4, =0x08000000 56 str r4, [r3, #0xc0] 65 ldr r4, [r3] 68 cmp r4, r3 73 cmp r4, r [all...] |
/u-boot/arch/arm/include/asm/arch-mx7ulp/ |
H A D | mx7ulp_plugin.S | 14 push {r0-r4, lr} 41 ldr r4, [r3] 43 ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET] 44 blx r4 53 pop {r0-r4, lr}
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/u-boot/arch/arm/mach-at91/ |
H A D | bootparams_atmel.S | 15 str r4, [r0, #0]
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/u-boot/arch/microblaze/cpu/ |
H A D | start.S | 112 SYM_ADDR(r4, r0, __bss_end) 113 cmp r6, r5, r4 118 cmp r6, r5, r4 /* check if we have reach the end */ 152 * r4: Stores the vector base address 158 swi r4, r1, 12 181 /* Store the vector base address in r4 */ 182 addi r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR 185 swi r2, r4, 0x0 /* reset address - imm opcode */ 186 swi r3, r4, 0x4 /* reset address - brai opcode */ 193 sh r7, r4, r [all...] |