1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2007 Michal Simek
4 * (C) Copyright 2004 Atmark Techno, Inc.
5 *
6 * Michal  SIMEK <monstr@monstr.eu>
7 * Yasushi SHOJI <yashi@atmark-techno.com>
8 */
9
10#include <asm-offsets.h>
11#include <config.h>
12
13#define SYM_ADDR(reg, reg_add, symbol)	\
14	mfs	r20, rpc; \
15	addik	r20, r20, _GLOBAL_OFFSET_TABLE_ + 8; \
16	lwi	reg, r20, symbol@GOT; \
17	addk	reg, reg reg_add;
18
19	.text
20	.global _start
21_start:
22	mts	rmsr, r0	/* disable cache */
23	mfs	r20, rpc
24	addi	r20, r20, -4
25
26	mts	rslr, r0
27	mts	rshr, r20
28
29#if defined(CONFIG_SPL_BUILD)
30	addi	r1, r0, CONFIG_SPL_STACK
31#else
32	add	r1, r0, r20
33	bri	1f
34
35	/* Force alignment for easier ASM code below */
36#define ALIGNMENT_ADDR	0x20
37	.align	4
38uboot_dyn_start:
39	.word	__rel_dyn_start
40
41uboot_dyn_end:
42	.word	__rel_dyn_end
43
44uboot_sym_start:
45	.word	__dyn_sym_start
461:
47
48	addi	r5, r20, 0
49	add	r6, r0, r0
50
51	lwi	r7, r20, ALIGNMENT_ADDR
52	addi	r7, r7, -CONFIG_TEXT_BASE
53	add	r7, r7, r5
54	lwi	r8, r20, ALIGNMENT_ADDR + 0x4
55	addi	r8, r8, -CONFIG_TEXT_BASE
56	add	r8, r8, r5
57	lwi	r9, r20, ALIGNMENT_ADDR + 0x8
58	addi	r9, r9, -CONFIG_TEXT_BASE
59	add	r9, r9, r5
60	addi	r10, r0, CONFIG_TEXT_BASE
61
62	brlid	r15, mb_fix_rela
63	nop
64#endif
65
66	addi	r1, r1, -4	/* Decrement SP to top of memory */
67
68	/* Call board_init_f_alloc_reserve with the current stack pointer as
69	 * parameter. */
70	add	r5, r0, r1
71	brlid	r15, board_init_f_alloc_reserve
72	nop
73
74	/* board_init_f_alloc_reserve returns a pointer to the allocated area
75	 * in r3. Set the new stack pointer below this area. */
76	add	r1, r0, r3
77	mts	rshr, r1
78	addi	r1, r1, -4
79
80	/* Call board_init_f_init_reserve with the address returned by
81	 * board_init_f_alloc_reserve as parameter. */
82	add	r5, r0, r3
83	brlid	r15, board_init_f_init_reserve
84	nop
85
86#if !defined(CONFIG_SPL_BUILD)
87	/* Setup vectors with pre-relocation symbols */
88	or	r5, r0, r0
89	brlid	r15, __setup_exceptions
90	nop
91#endif
92
93	/*
94	 * Initialize global data cpuinfo with default values (cache
95	 * size, cache line size, etc).
96	 */
97	brlid	r15, microblaze_early_cpuinfo_init
98	nop
99
100	/* Flush cache before enable cache */
101	brlid	r15, flush_cache_all
102	nop
103
104	/* enable instruction and data cache */
105	mfs	r12, rmsr
106	ori	r12, r12, 0x1a0
107	mts	rmsr, r12
108
109clear_bss:
110	/* clear BSS segments */
111	SYM_ADDR(r5, r0, __bss_start)
112	SYM_ADDR(r4, r0, __bss_end)
113	cmp	r6, r5, r4
114	beqi	r6, 3f
1152:
116	swi     r0, r5, 0 /* write zero to loc */
117	addi    r5, r5, 4 /* increment to next loc */
118	cmp     r6, r5, r4 /* check if we have reach the end */
119	bnei    r6, 2b
1203:	/* jumping to board_init */
121#ifdef CONFIG_DEBUG_UART
122	brlid	r15, debug_uart_init
123	nop
124#endif
125#ifndef CONFIG_SPL_BUILD
126	or	r5, r0, r0	/* flags - empty */
127	bri	board_init_f
128#else
129	bri	board_init_r
130#endif
1311:	bri	1b
132
133#ifndef CONFIG_SPL_BUILD
134	.text
135	.ent	__setup_exceptions
136	.align	2
137/*
138 * Set up reset, interrupt, user exception and hardware exception vectors.
139 *
140 * Parameters:
141 * r5 - relocation offset (zero when setting up vectors before
142 *      relocation, and gd->reloc_off when setting up vectors after
143 *      relocation)
144 *    - the relocation offset is added to the _exception_handler,
145 *      _interrupt_handler and _hw_exception_handler symbols to reflect the
146 *      post-relocation memory addresses
147 *
148 * Reserve registers:
149 * r10: Stores little/big endian offset for vectors
150 * r2: Stores imm opcode
151 * r3: Stores brai opcode
152 * r4: Stores the vector base address
153 */
154__setup_exceptions:
155	addik	r1, r1, -32
156	swi	r2, r1, 4
157	swi	r3, r1, 8
158	swi	r4, r1, 12
159	swi	r6, r1, 16
160	swi	r7, r1, 20
161	swi	r8, r1, 24
162	swi	r10, r1, 28
163
164	/* Find-out if u-boot is running on BIG/LITTLE endian platform
165	 * There are some steps which is necessary to keep in mind:
166	 * 1. Setup offset value to r6
167	 * 2. Store word offset value to address 0x0
168	 * 3. Load just byte from address 0x0
169	 * 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
170	 *     value that's why is on address 0x0
171	 * 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
172	 */
173	addik	r6, r0, 0x2 /* BIG/LITTLE endian offset */
174	sw	r6, r1, r0
175	lbu	r10, r1, r0
176
177	/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
178	addi	r2, r0, 0xb0000000	/* hex b000 opcode imm */
179	addi	r3, r0, 0xb8080000	/* hew b808 opcode brai */
180
181	/* Store the vector base address in r4 */
182	addi	r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
183
184	/* reset address */
185	swi	r2, r4, 0x0	/* reset address - imm opcode */
186	swi	r3, r4, 0x4	/* reset address - brai opcode */
187
188	SYM_ADDR(r6, r0, _start)
189	/* Intentionally keep reset vector back to origin u-boot location */
190	sw	r6, r1, r0
191	lhu	r7, r1, r10
192	rsubi	r8, r10, 0x2
193	sh	r7, r4, r8
194	rsubi	r8, r10, 0x6
195	sh	r6, r4, r8
196
197#if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
198	/* user_vector_exception */
199	swi	r2, r4, 0x8	/* user vector exception - imm opcode */
200	swi	r3, r4, 0xC	/* user vector exception - brai opcode */
201
202	SYM_ADDR(r6, r5, _exception_handler)
203	sw	r6, r1, r0
204	/*
205	 * BIG ENDIAN memory map for user exception
206	 * 0x8: 0xB000XXXX
207	 * 0xC: 0xB808XXXX
208	 *
209	 * then it is necessary to count address for storing the most significant
210	 * 16bits from _exception_handler address and copy it to
211	 * 0xa address. Big endian use offset in r10=0 that's why is it just
212	 * 0xa address. The same is done for the least significant 16 bits
213	 * for 0xe address.
214	 *
215	 * LITTLE ENDIAN memory map for user exception
216	 * 0x8: 0xXXXX00B0
217	 * 0xC: 0xXXXX08B8
218	 *
219	 * Offset is for little endian setup to 0x2. rsubi instruction decrease
220	 * address value to ensure that points to proper place which is
221	 * 0x8 for the most significant 16 bits and
222	 * 0xC for the least significant 16 bits
223	 */
224	lhu	r7, r1, r10
225	rsubi	r8, r10, 0xa
226	sh	r7, r4, r8
227	rsubi	r8, r10, 0xe
228	sh	r6, r4, r8
229#endif
230
231	/* interrupt_handler */
232	swi	r2, r4, 0x10	/* interrupt - imm opcode */
233	swi	r3, r4, 0x14	/* interrupt - brai opcode */
234
235	SYM_ADDR(r6, r5, _interrupt_handler)
236	sw	r6, r1, r0
237	lhu	r7, r1, r10
238	rsubi	r8, r10, 0x12
239	sh	r7, r4, r8
240	rsubi	r8, r10, 0x16
241	sh	r6, r4, r8
242
243	/* hardware exception */
244	swi	r2, r4, 0x20	/* hardware exception - imm opcode */
245	swi	r3, r4, 0x24	/* hardware exception - brai opcode */
246
247	SYM_ADDR(r6, r5, _hw_exception_handler)
248	sw	r6, r1, r0
249	lhu	r7, r1, r10
250	rsubi	r8, r10, 0x22
251	sh	r7, r4, r8
252	rsubi	r8, r10, 0x26
253	sh	r6, r4, r8
254
255	lwi	r10, r1, 28
256	lwi	r8, r1, 24
257	lwi	r7, r1, 20
258	lwi	r6, r1, 16
259	lwi	r4, r1, 12
260	lwi	r3, r1, 8
261	lwi	r2, r1, 4
262	addik	r1, r1, 32
263
264	rtsd	r15, 8
265	or	r0, r0, r0
266	.end	__setup_exceptions
267
268/*
269 * Relocate u-boot
270 */
271	.text
272	.global	relocate_code
273	.ent	relocate_code
274	.align	2
275relocate_code:
276	/*
277	 * r5 - start_addr_sp
278	 * r6 - new_gd
279	 * r7 - reloc_addr
280	 */
281	addi	r1, r5, 0 /* Start to use new SP */
282	mts	rshr, r1
283	addi	r31, r6, 0 /* Start to use new GD */
284
285	/* Relocate text and data - r12 temp value */
286	SYM_ADDR(r21, r0, _start)
287	SYM_ADDR(r22, r0, _end) /* Include BSS too */
288	addi	r22, r22, -4
289
290	rsub	r6, r21, r22
291	or	r5, r0, r0
2921:	lw	r12, r21, r5 /* Load u-boot data */
293	sw	r12, r7, r5 /* Write zero to loc */
294	cmp	r12, r5, r6 /* Check if we have reach the end */
295	bneid	r12, 1b
296	addi	r5, r5, 4 /* Increment to next loc - relocate code */
297
298	/* R23 points to the base address. */
299	rsub	r23, r21, r7 /* keep - this is already here gd->reloc_off */
300
301	/* Setup vectors with post-relocation symbols */
302	add	r5, r0, r23 /* load gd->reloc_off to r5 */
303	brlid	r15, __setup_exceptions
304	nop
305
306	/* reloc_offset is current location */
307	SYM_ADDR(r10, r0, _start)
308
309	/* r5 new address where I should copy code */
310	add	r5, r0, r7 /* Move reloc addr to r5 */
311
312	/* Verbose message */
313	addi	r6, r0, 0
314
315	SYM_ADDR(r7, r0, __rel_dyn_start)
316	rsub	r7, r10, r7
317	add	r7, r7, r5
318	SYM_ADDR(r8, r0, __rel_dyn_end)
319	rsub	r8, r10, r8
320	add	r8, r8, r5
321	SYM_ADDR(r9, r0, __dyn_sym_start)
322	rsub	r9, r10, r9
323	add	r9, r9, r5
324	brlid	r15, mb_fix_rela
325	nop
326	/* end of code which does relocation */
327
328	/* Flush caches to ensure consistency */
329	brlid	r15, flush_cache_all
330	nop
331
3322:	addi	r5, r31, 0 /* gd is initialized in board_r.c */
333	SYM_ADDR(r6, r0, _start)
334	SYM_ADDR(r12, r23, board_init_r)
335	bra	r12 /* Jump to relocated code */
336
337	.end	relocate_code
338#endif
339