Searched refs:ports (Results 1 - 25 of 32) sorted by relevance

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/u-boot/arch/arm/dts/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/arch/xtensa/dts/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/arch/sandbox/dts/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/arch/nios2/dts/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/arch/microblaze/dts/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/arch/x86/dts/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/arch/mips/dts/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/dts/upstream/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/include/dt-bindings/sound/
H A Dqcom,q6afe.h7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/u-boot/include/xen/interface/
H A Dsched.h73 * Poll a set of event-channel ports. Return when one or more are pending. An
123 GUEST_HANDLE(evtchn_port_t)ports; member in struct:sched_poll
/u-boot/drivers/net/mscc_eswitch/
H A Dluton_switch.c179 struct luton_phy_port_t ports[MAX_PORT];
226 /* Enable IFH insertion/parsing on CPU ports */
424 if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
427 mask = BIT(priv->ports[i].serdes_index);
428 serdes6g_setup(priv->regs[HSIO], mask, priv->ports[i].phy_mode);
468 * Put front ports in "port isolation modes" - i.e. they can't send
469 * to other ports - via the PGID sorce masks.
579 priv->ports[index].phy_addr = phy_addr;
580 priv->ports[inde
180 struct luton_phy_port_t ports[MAX_PORT]; member in struct:luton_private
[all...]
H A Docelot_switch.c163 struct ocelot_phy_port_t ports[MAX_PORT];
227 /* Enable IFH insertion/parsing on CPU ports */
357 if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
360 mask = BIT(priv->ports[i].serdes_index);
362 priv->ports[i].phy_mode);
397 * Put fron ports in "port isolation modes" - i.e. they cant send
398 * to other ports - via the PGID sorce masks.
517 priv->ports[index].phy_addr = phy_addr;
518 priv->ports[inde
164 struct ocelot_phy_port_t ports[MAX_PORT]; member in struct:ocelot_private
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H A Dserval_switch.c148 struct serval_phy_port_t ports[MAX_PORT];
190 /* Enable IFH insertion/parsing on CPU ports */
317 if (!priv->ports[i].bus)
320 mask = BIT(priv->ports[i].serdes_index);
322 priv->ports[i].phy_mode);
474 priv->ports[index].phy_addr = phy_addr;
475 priv->ports[index].bus = bus;
476 priv->ports[index].serdes_index = serdes_index;
477 priv->ports[index].phy_mode = phy_mode;
510 /* iterate all the ports an
149 struct serval_phy_port_t ports[MAX_PORT]; member in struct:serval_private
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H A Djr2_switch.c271 struct jr2_phy_port_t ports[MAX_PORT];
761 if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff)
764 mask = BIT(priv->ports[i].serdes_index);
765 if (priv->ports[i].serdes_index < SERDES1G_MAX) {
767 priv->ports[i].phy_mode);
771 priv->ports[i].phy_mode);
854 priv->ports[index].phy_addr = phy_addr;
855 priv->ports[index].bus = bus;
856 priv->ports[inde
272 struct jr2_phy_port_t ports[MAX_PORT]; member in struct:jr2_private
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H A Dservalt_switch.c125 struct servalt_phy_port_t ports[MAX_PORT];
406 priv->ports[index].phy_addr = phy_addr;
407 priv->ports[index].bus = bus;
440 /* iterate all the ports and find out on which bus they are */
481 if (!priv->ports[i].bus)
484 phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev,
126 struct servalt_phy_port_t ports[MAX_PORT]; member in struct:servalt_private
/u-boot/drivers/gpio/
H A Dtegra186_gpio.c24 const struct tegra186_gpio_port_data *ports;
189 plat->name = ctlr_data->ports[port].name;
190 plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
206 /* Only child devices have ports */
243 .ports = tegra186_gpio_main_ports,
259 .ports = tegra186_gpio_aon_ports,
25 const struct tegra186_gpio_port_data *ports; member in struct:tegra186_gpio_ctlr_data
H A Dmscc_sgpio.c75 u32 ports;
213 priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
250 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
76 u32 ports; member in struct:mscc_sgpio_priv
/u-boot/board/Marvell/mvebu_armada-37xx/
H A Dboard.c352 * Restrict output to ports 1,2,3 only from port 0 (CPU)
536 const char *ports[] = { "downlink", "uplink" }; local
567 * MAC-s for Uplink and Downlink ports are stored under
572 if (eth_env_get_enetaddr(ports[i], mac)) {
575 ports[i],
576 strlen(ports[i]) + 1,
582 ports[i],
583 strlen(ports[i]) + 1,
/u-boot/drivers/pci/
H A Dpcie_mediatek.c139 struct list_head ports;
269 list_for_each_entry(port, &pcie->ports, list) {
560 list_add_tail(&port->list, &pcie->ports);
629 list_add_tail(&port->list, &pcie->ports);
641 INIT_LIST_HEAD(&pcie->ports);
675 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
690 INIT_LIST_HEAD(&pcie->ports);
713 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
140 struct list_head ports; member in struct:mtk_pcie
H A Dpcie_apple.c146 struct list_head ports;
313 list_add_tail(&port->entry, &pcie->ports);
353 INIT_LIST_HEAD(&pcie->ports);
375 list_for_each_entry_safe(port, tmp, &pcie->ports, entry) {
147 struct list_head ports; member in struct:apple_pcie_priv
/u-boot/arch/mips/mach-octeon/
H A Dcvmx-helper-xaui.c53 /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
63 * Probe a XAUI interface and determine the number of ports
69 * @return Number of ports on the interface. Zero to disable.
73 int i, ports; local
125 ports = __cvmx_helper_xaui_enumerate(xiface);
127 if (ports <= 0)
142 * Setup PKO to support 16 ports for HiGig2 virtual
143 * ports. We're pointing all of the PKO packet ports
157 /* All PKO ports ma
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H A Dcvmx-helper.c48 #include <mach/cvmx-pko-internal-ports-range.h>
62 * @param enumerate Method the get number of interface ports.
65 * connected ports.
322 * configured as mixed mode, some ports are sgmii and some are xfi.
357 * gets the number of its ports.
503 * may have multiple ports. Most chips support two interfaces,
536 int ports; local
541 ports = cvmx_helper_interface_enumerate(interface);
542 ports = __cvmx_helper_board_interface_probe(interface, ports);
1308 int interface, xiface, ports; local
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H A Dcvmx-helper-sgmii.c376 * @param num_ports Number of ports on the interface
457 * Probe a SGMII interface and determine the number of ports
463 * @return Number of ports on the interface. Zero to disable.
470 int ports; local
484 ports = __cvmx_helper_sgmii_enumerate(xiface);
486 if (ports <= 0)
498 return ports;
H A DMakefile48 obj-y += cvmx-pko-internal-ports-range.o
/u-boot/drivers/net/ti/
H A Dam65-cpsw-nuss.c119 struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS];
192 struct am65_cpsw_port *port = &common->ports[priv->port_id];
325 struct am65_cpsw_port *port = &common->ports[priv->port_id];
326 struct am65_cpsw_port *port0 = &common->ports[0];
460 /* disable ports */
543 struct am65_cpsw_port *port = &common->ports[priv->port_id];
729 ports_np = dev_read_subnode(dev, "ethernet-ports");
762 cpsw_common->ports[port_id].disabled = disabled;
772 struct am65_cpsw_port *port = &cpsw_common->ports[i];
120 struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS]; member in struct:am65_cpsw_common

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