/u-boot/arch/arm/dts/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/arch/xtensa/dts/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/arch/sandbox/dts/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/arch/nios2/dts/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/arch/microblaze/dts/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/arch/x86/dts/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/arch/mips/dts/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/dts/upstream/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/include/dt-bindings/sound/ |
H A D | qcom,q6afe.h | 7 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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/u-boot/include/xen/interface/ |
H A D | sched.h | 73 * Poll a set of event-channel ports. Return when one or more are pending. An 123 GUEST_HANDLE(evtchn_port_t)ports; member in struct:sched_poll
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/u-boot/drivers/net/mscc_eswitch/ |
H A D | luton_switch.c | 179 struct luton_phy_port_t ports[MAX_PORT]; 226 /* Enable IFH insertion/parsing on CPU ports */ 424 if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff) 427 mask = BIT(priv->ports[i].serdes_index); 428 serdes6g_setup(priv->regs[HSIO], mask, priv->ports[i].phy_mode); 468 * Put front ports in "port isolation modes" - i.e. they can't send 469 * to other ports - via the PGID sorce masks. 579 priv->ports[index].phy_addr = phy_addr; 580 priv->ports[inde 180 struct luton_phy_port_t ports[MAX_PORT]; member in struct:luton_private [all...] |
H A D | ocelot_switch.c | 163 struct ocelot_phy_port_t ports[MAX_PORT]; 227 /* Enable IFH insertion/parsing on CPU ports */ 357 if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff) 360 mask = BIT(priv->ports[i].serdes_index); 362 priv->ports[i].phy_mode); 397 * Put fron ports in "port isolation modes" - i.e. they cant send 398 * to other ports - via the PGID sorce masks. 517 priv->ports[index].phy_addr = phy_addr; 518 priv->ports[inde 164 struct ocelot_phy_port_t ports[MAX_PORT]; member in struct:ocelot_private [all...] |
H A D | serval_switch.c | 148 struct serval_phy_port_t ports[MAX_PORT]; 190 /* Enable IFH insertion/parsing on CPU ports */ 317 if (!priv->ports[i].bus) 320 mask = BIT(priv->ports[i].serdes_index); 322 priv->ports[i].phy_mode); 474 priv->ports[index].phy_addr = phy_addr; 475 priv->ports[index].bus = bus; 476 priv->ports[index].serdes_index = serdes_index; 477 priv->ports[index].phy_mode = phy_mode; 510 /* iterate all the ports an 149 struct serval_phy_port_t ports[MAX_PORT]; member in struct:serval_private [all...] |
H A D | jr2_switch.c | 271 struct jr2_phy_port_t ports[MAX_PORT]; 761 if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff) 764 mask = BIT(priv->ports[i].serdes_index); 765 if (priv->ports[i].serdes_index < SERDES1G_MAX) { 767 priv->ports[i].phy_mode); 771 priv->ports[i].phy_mode); 854 priv->ports[index].phy_addr = phy_addr; 855 priv->ports[index].bus = bus; 856 priv->ports[inde 272 struct jr2_phy_port_t ports[MAX_PORT]; member in struct:jr2_private [all...] |
H A D | servalt_switch.c | 125 struct servalt_phy_port_t ports[MAX_PORT]; 406 priv->ports[index].phy_addr = phy_addr; 407 priv->ports[index].bus = bus; 440 /* iterate all the ports and find out on which bus they are */ 481 if (!priv->ports[i].bus) 484 phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev, 126 struct servalt_phy_port_t ports[MAX_PORT]; member in struct:servalt_private
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/u-boot/drivers/gpio/ |
H A D | tegra186_gpio.c | 24 const struct tegra186_gpio_port_data *ports; 189 plat->name = ctlr_data->ports[port].name; 190 plat->regs = &(regs[ctlr_data->ports[port].offset / 4]); 206 /* Only child devices have ports */ 243 .ports = tegra186_gpio_main_ports, 259 .ports = tegra186_gpio_aon_ports, 25 const struct tegra186_gpio_port_data *ports; member in struct:tegra186_gpio_ctlr_data
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H A D | mscc_sgpio.c | 75 u32 ports; 213 priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF); 250 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); 76 u32 ports; member in struct:mscc_sgpio_priv
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/u-boot/board/Marvell/mvebu_armada-37xx/ |
H A D | board.c | 352 * Restrict output to ports 1,2,3 only from port 0 (CPU) 536 const char *ports[] = { "downlink", "uplink" }; local 567 * MAC-s for Uplink and Downlink ports are stored under 572 if (eth_env_get_enetaddr(ports[i], mac)) { 575 ports[i], 576 strlen(ports[i]) + 1, 582 ports[i], 583 strlen(ports[i]) + 1,
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/u-boot/drivers/pci/ |
H A D | pcie_mediatek.c | 139 struct list_head ports; 269 list_for_each_entry(port, &pcie->ports, list) { 560 list_add_tail(&port->list, &pcie->ports); 629 list_add_tail(&port->list, &pcie->ports); 641 INIT_LIST_HEAD(&pcie->ports); 675 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 690 INIT_LIST_HEAD(&pcie->ports); 713 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 140 struct list_head ports; member in struct:mtk_pcie
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H A D | pcie_apple.c | 146 struct list_head ports; 313 list_add_tail(&port->entry, &pcie->ports); 353 INIT_LIST_HEAD(&pcie->ports); 375 list_for_each_entry_safe(port, tmp, &pcie->ports, entry) { 147 struct list_head ports; member in struct:apple_pcie_priv
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/u-boot/arch/mips/mach-octeon/ |
H A D | cvmx-helper-xaui.c | 53 /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ 63 * Probe a XAUI interface and determine the number of ports 69 * @return Number of ports on the interface. Zero to disable. 73 int i, ports; local 125 ports = __cvmx_helper_xaui_enumerate(xiface); 127 if (ports <= 0) 142 * Setup PKO to support 16 ports for HiGig2 virtual 143 * ports. We're pointing all of the PKO packet ports 157 /* All PKO ports ma [all...] |
H A D | cvmx-helper.c | 48 #include <mach/cvmx-pko-internal-ports-range.h> 62 * @param enumerate Method the get number of interface ports. 65 * connected ports. 322 * configured as mixed mode, some ports are sgmii and some are xfi. 357 * gets the number of its ports. 503 * may have multiple ports. Most chips support two interfaces, 536 int ports; local 541 ports = cvmx_helper_interface_enumerate(interface); 542 ports = __cvmx_helper_board_interface_probe(interface, ports); 1308 int interface, xiface, ports; local [all...] |
H A D | cvmx-helper-sgmii.c | 376 * @param num_ports Number of ports on the interface 457 * Probe a SGMII interface and determine the number of ports 463 * @return Number of ports on the interface. Zero to disable. 470 int ports; local 484 ports = __cvmx_helper_sgmii_enumerate(xiface); 486 if (ports <= 0) 498 return ports;
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H A D | Makefile | 48 obj-y += cvmx-pko-internal-ports-range.o
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/u-boot/drivers/net/ti/ |
H A D | am65-cpsw-nuss.c | 119 struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS]; 192 struct am65_cpsw_port *port = &common->ports[priv->port_id]; 325 struct am65_cpsw_port *port = &common->ports[priv->port_id]; 326 struct am65_cpsw_port *port0 = &common->ports[0]; 460 /* disable ports */ 543 struct am65_cpsw_port *port = &common->ports[priv->port_id]; 729 ports_np = dev_read_subnode(dev, "ethernet-ports"); 762 cpsw_common->ports[port_id].disabled = disabled; 772 struct am65_cpsw_port *port = &cpsw_common->ports[i]; 120 struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS]; member in struct:am65_cpsw_common
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