1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 4 * 5 * Copyright (C) 2019, Texas Instruments, Incorporated 6 * 7 */ 8 9#include <common.h> 10#include <malloc.h> 11#include <asm/cache.h> 12#include <asm/gpio.h> 13#include <asm/io.h> 14#include <asm/processor.h> 15#include <clk.h> 16#include <dm.h> 17#include <dm/device_compat.h> 18#include <dm/lists.h> 19#include <dm/pinctrl.h> 20#include <dma-uclass.h> 21#include <dm/of_access.h> 22#include <miiphy.h> 23#include <net.h> 24#include <phy.h> 25#include <power-domain.h> 26#include <regmap.h> 27#include <soc.h> 28#include <syscon.h> 29#include <linux/bitops.h> 30#include <linux/delay.h> 31#include <linux/printk.h> 32#include <linux/soc/ti/ti-udma.h> 33 34#define AM65_CPSW_CPSWNU_MAX_PORTS 9 35 36#define AM65_CPSW_SS_BASE 0x0 37#define AM65_CPSW_SGMII_BASE 0x100 38#define AM65_CPSW_MDIO_BASE 0xf00 39#define AM65_CPSW_XGMII_BASE 0x2100 40#define AM65_CPSW_CPSW_NU_BASE 0x20000 41#define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000 42 43#define AM65_CPSW_CPSW_NU_PORTS_OFFSET 0x1000 44#define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET 0x330 45 46#define AM65_CPSW_MDIO_BUS_FREQ_DEF 1000000 47 48#define AM65_CPSW_CTL_REG 0x4 49#define AM65_CPSW_STAT_PORT_EN_REG 0x14 50#define AM65_CPSW_PTYPE_REG 0x18 51 52#define AM65_CPSW_CTL_REG_P0_ENABLE BIT(2) 53#define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE BIT(13) 54#define AM65_CPSW_CTL_REG_P0_RX_PAD BIT(14) 55 56#define AM65_CPSW_P0_FLOW_ID_REG 0x8 57#define AM65_CPSW_PN_RX_MAXLEN_REG 0x24 58#define AM65_CPSW_PN_REG_SA_L 0x308 59#define AM65_CPSW_PN_REG_SA_H 0x30c 60 61#define AM65_CPSW_SGMII_CONTROL_REG 0x010 62#define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 63#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 64 65#define ADVERTISE_SGMII 0x1 66 67#define AM65_CPSW_ALE_CTL_REG 0x8 68#define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31) 69#define AM65_CPSW_ALE_CTL_REG_RESET_TBL BIT(30) 70#define AM65_CPSW_ALE_CTL_REG_BYPASS BIT(4) 71#define AM65_CPSW_ALE_PN_CTL_REG(x) (0x40 + (x) * 4) 72#define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD 0x3 73#define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY BIT(11) 74 75#define AM65_CPSW_ALE_THREADMAPDEF_REG 0x134 76#define AM65_CPSW_ALE_DEFTHREAD_EN BIT(15) 77 78#define AM65_CPSW_MACSL_CTL_REG 0x0 79#define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15) 80#define AM65_CPSW_MACSL_CTL_EXT_EN BIT(18) 81#define AM65_CPSW_MACSL_CTL_REG_GIG BIT(7) 82#define AM65_CPSW_MACSL_CTL_REG_GMII_EN BIT(5) 83#define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1) 84#define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX BIT(0) 85#define AM65_CPSW_MACSL_RESET_REG 0x8 86#define AM65_CPSW_MACSL_RESET_REG_RESET BIT(0) 87#define AM65_CPSW_MACSL_STATUS_REG 0x4 88#define AM65_CPSW_MACSL_RESET_REG_PN_IDLE BIT(31) 89#define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE BIT(30) 90#define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE BIT(29) 91#define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE BIT(28) 92#define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \ 93 (AM65_CPSW_MACSL_RESET_REG_PN_IDLE | \ 94 AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE | \ 95 AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE | \ 96 AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE) 97 98#define AM65_CPSW_CPPI_PKT_TYPE 0x7 99 100#define DEFAULT_GPIO_RESET_DELAY 10 101 102struct am65_cpsw_port { 103 fdt_addr_t port_base; 104 fdt_addr_t port_sgmii_base; 105 fdt_addr_t macsl_base; 106 bool disabled; 107 u32 mac_control; 108}; 109 110struct am65_cpsw_common { 111 struct udevice *dev; 112 fdt_addr_t ss_base; 113 fdt_addr_t cpsw_base; 114 fdt_addr_t ale_base; 115 116 struct clk fclk; 117 struct power_domain pwrdmn; 118 119 u32 port_num; 120 struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS]; 121 122 u32 bus_freq; 123 124 struct dma dma_tx; 125 struct dma dma_rx; 126 u32 rx_next; 127 u32 rx_pend; 128 bool started; 129}; 130 131struct am65_cpsw_priv { 132 struct udevice *dev; 133 struct am65_cpsw_common *cpsw_common; 134 u32 port_id; 135 struct phy_device *phydev; 136}; 137 138#ifdef PKTSIZE_ALIGN 139#define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN 140#else 141#define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN) 142#endif 143 144#ifdef PKTBUFSRX 145#define UDMA_RX_DESC_NUM PKTBUFSRX 146#else 147#define UDMA_RX_DESC_NUM 4 148#endif 149 150#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 151 ((mac)[2] << 16) | ((mac)[3] << 24)) 152#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 153 154static void am65_cpsw_set_sl_mac(struct am65_cpsw_port *slave, 155 unsigned char *addr) 156{ 157 writel(mac_hi(addr), 158 slave->port_base + AM65_CPSW_PN_REG_SA_H); 159 writel(mac_lo(addr), 160 slave->port_base + AM65_CPSW_PN_REG_SA_L); 161} 162 163int am65_cpsw_macsl_reset(struct am65_cpsw_port *slave) 164{ 165 u32 i = 100; 166 167 /* Set the soft reset bit */ 168 writel(AM65_CPSW_MACSL_RESET_REG_RESET, 169 slave->macsl_base + AM65_CPSW_MACSL_RESET_REG); 170 171 while ((readl(slave->macsl_base + AM65_CPSW_MACSL_RESET_REG) & 172 AM65_CPSW_MACSL_RESET_REG_RESET) && i--) 173 cpu_relax(); 174 175 /* Timeout on the reset */ 176 return i; 177} 178 179static int am65_cpsw_macsl_wait_for_idle(struct am65_cpsw_port *slave) 180{ 181 u32 i = 100; 182 183 while ((readl(slave->macsl_base + AM65_CPSW_MACSL_STATUS_REG) & 184 AM65_CPSW_MACSL_RESET_REG_IDLE_MASK) && i--) 185 cpu_relax(); 186 187 return i; 188} 189 190static int am65_cpsw_update_link(struct am65_cpsw_priv *priv) 191{ 192 struct am65_cpsw_common *common = priv->cpsw_common; 193 struct am65_cpsw_port *port = &common->ports[priv->port_id]; 194 struct phy_device *phy = priv->phydev; 195 u32 mac_control = 0; 196 197 if (phy->link) { /* link up */ 198 mac_control = /*AM65_CPSW_MACSL_CTL_REG_LOOPBACK |*/ 199 AM65_CPSW_MACSL_CTL_REG_GMII_EN; 200 if (phy->speed == 1000) 201 mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG; 202 if (phy->speed == 10 && phy_interface_is_rgmii(phy)) 203 /* Can be used with in band mode only */ 204 mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN; 205 if (phy->duplex == DUPLEX_FULL) 206 mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX; 207 if (phy->speed == 100) 208 mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A; 209 if (phy->interface == PHY_INTERFACE_MODE_SGMII) 210 mac_control |= AM65_CPSW_MACSL_CTL_EXT_EN; 211 } 212 213 if (mac_control == port->mac_control) 214 goto out; 215 216 if (mac_control) { 217 printf("link up on port %d, speed %d, %s duplex\n", 218 priv->port_id, phy->speed, 219 (phy->duplex == DUPLEX_FULL) ? "full" : "half"); 220 } else { 221 printf("link down on port %d\n", priv->port_id); 222 } 223 224 writel(mac_control, port->macsl_base + AM65_CPSW_MACSL_CTL_REG); 225 port->mac_control = mac_control; 226 227out: 228 return phy->link; 229} 230 231#define AM65_GMII_SEL_PORT_OFFS(x) (0x4 * ((x) - 1)) 232 233#define AM65_GMII_SEL_MODE_MII 0 234#define AM65_GMII_SEL_MODE_RMII 1 235#define AM65_GMII_SEL_MODE_RGMII 2 236#define AM65_GMII_SEL_MODE_SGMII 3 237 238#define AM65_GMII_SEL_RGMII_IDMODE BIT(4) 239 240static int am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv, 241 phy_interface_t phy_mode) 242{ 243 struct udevice *dev = priv->dev; 244 u32 offset, reg, phandle; 245 bool rgmii_id = false; 246 fdt_addr_t gmii_sel; 247 u32 mode = 0; 248 ofnode node; 249 int ret; 250 251 ret = ofnode_read_u32(dev_ofnode(dev), "phys", &phandle); 252 if (ret) 253 return ret; 254 255 ret = ofnode_read_u32_index(dev_ofnode(dev), "phys", 1, &offset); 256 if (ret) 257 return ret; 258 259 node = ofnode_get_by_phandle(phandle); 260 if (!ofnode_valid(node)) 261 return -ENODEV; 262 263 gmii_sel = ofnode_get_addr(node); 264 if (gmii_sel == FDT_ADDR_T_NONE) 265 return -ENODEV; 266 267 gmii_sel += AM65_GMII_SEL_PORT_OFFS(offset); 268 reg = readl(gmii_sel); 269 270 dev_dbg(dev, "old gmii_sel: %08x\n", reg); 271 272 switch (phy_mode) { 273 case PHY_INTERFACE_MODE_RMII: 274 mode = AM65_GMII_SEL_MODE_RMII; 275 break; 276 277 case PHY_INTERFACE_MODE_RGMII: 278 case PHY_INTERFACE_MODE_RGMII_RXID: 279 mode = AM65_GMII_SEL_MODE_RGMII; 280 break; 281 282 case PHY_INTERFACE_MODE_RGMII_ID: 283 case PHY_INTERFACE_MODE_RGMII_TXID: 284 mode = AM65_GMII_SEL_MODE_RGMII; 285 rgmii_id = true; 286 break; 287 288 case PHY_INTERFACE_MODE_SGMII: 289 mode = AM65_GMII_SEL_MODE_SGMII; 290 break; 291 292 default: 293 dev_warn(dev, 294 "Unsupported PHY mode: %u. Defaulting to MII.\n", 295 phy_mode); 296 /* fallthrough */ 297 case PHY_INTERFACE_MODE_MII: 298 mode = AM65_GMII_SEL_MODE_MII; 299 break; 300 }; 301 302 if (rgmii_id) 303 mode |= AM65_GMII_SEL_RGMII_IDMODE; 304 305 reg = mode; 306 dev_dbg(dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n", 307 phy_mode, reg); 308 writel(reg, gmii_sel); 309 310 reg = readl(gmii_sel); 311 if (reg != mode) { 312 dev_err(dev, 313 "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n", 314 mode, reg); 315 return 0; 316 } 317 318 return 0; 319} 320 321static int am65_cpsw_start(struct udevice *dev) 322{ 323 struct eth_pdata *pdata = dev_get_plat(dev); 324 struct am65_cpsw_priv *priv = dev_get_priv(dev); 325 struct am65_cpsw_common *common = priv->cpsw_common; 326 struct am65_cpsw_port *port = &common->ports[priv->port_id]; 327 struct am65_cpsw_port *port0 = &common->ports[0]; 328 struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data; 329 int ret, i; 330 331 ret = power_domain_on(&common->pwrdmn); 332 if (ret) { 333 dev_err(dev, "power_domain_on() failed %d\n", ret); 334 goto out; 335 } 336 337 ret = clk_enable(&common->fclk); 338 if (ret) { 339 dev_err(dev, "clk enabled failed %d\n", ret); 340 goto err_off_pwrdm; 341 } 342 343 common->rx_next = 0; 344 common->rx_pend = 0; 345 ret = dma_get_by_name(common->dev, "tx0", &common->dma_tx); 346 if (ret) { 347 dev_err(dev, "TX dma get failed %d\n", ret); 348 goto err_off_clk; 349 } 350 ret = dma_get_by_name(common->dev, "rx", &common->dma_rx); 351 if (ret) { 352 dev_err(dev, "RX dma get failed %d\n", ret); 353 goto err_free_tx; 354 } 355 356 for (i = 0; i < UDMA_RX_DESC_NUM; i++) { 357 ret = dma_prepare_rcv_buf(&common->dma_rx, 358 net_rx_packets[i], 359 UDMA_RX_BUF_SIZE); 360 if (ret) { 361 dev_err(dev, "RX dma add buf failed %d\n", ret); 362 goto err_free_tx; 363 } 364 } 365 366 ret = dma_enable(&common->dma_tx); 367 if (ret) { 368 dev_err(dev, "TX dma_enable failed %d\n", ret); 369 goto err_free_rx; 370 } 371 ret = dma_enable(&common->dma_rx); 372 if (ret) { 373 dev_err(dev, "RX dma_enable failed %d\n", ret); 374 goto err_dis_tx; 375 } 376 377 /* Control register */ 378 writel(AM65_CPSW_CTL_REG_P0_ENABLE | 379 AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE | 380 AM65_CPSW_CTL_REG_P0_RX_PAD, 381 common->cpsw_base + AM65_CPSW_CTL_REG); 382 383 /* disable priority elevation */ 384 writel(0, common->cpsw_base + AM65_CPSW_PTYPE_REG); 385 386 /* enable statistics */ 387 writel(BIT(0) | BIT(priv->port_id), 388 common->cpsw_base + AM65_CPSW_STAT_PORT_EN_REG); 389 390 /* Port 0 length register */ 391 writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG); 392 393 /* set base flow_id */ 394 dma_get_cfg(&common->dma_rx, 0, (void **)&dma_rx_cfg_data); 395 writel(dma_rx_cfg_data->flow_id_base, 396 port0->port_base + AM65_CPSW_P0_FLOW_ID_REG); 397 dev_info(dev, "K3 CPSW: rflow_id_base: %u\n", 398 dma_rx_cfg_data->flow_id_base); 399 400 /* Reset and enable the ALE */ 401 writel(AM65_CPSW_ALE_CTL_REG_ENABLE | AM65_CPSW_ALE_CTL_REG_RESET_TBL | 402 AM65_CPSW_ALE_CTL_REG_BYPASS, 403 common->ale_base + AM65_CPSW_ALE_CTL_REG); 404 405 /* port 0 put into forward mode */ 406 writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD, 407 common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0)); 408 409 writel(AM65_CPSW_ALE_DEFTHREAD_EN, 410 common->ale_base + AM65_CPSW_ALE_THREADMAPDEF_REG); 411 412 /* PORT x configuration */ 413 414 /* Port x Max length register */ 415 writel(PKTSIZE_ALIGN, port->port_base + AM65_CPSW_PN_RX_MAXLEN_REG); 416 417 /* Port x set mac */ 418 am65_cpsw_set_sl_mac(port, pdata->enetaddr); 419 420 /* Port x ALE: mac_only, Forwarding */ 421 writel(AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY | 422 AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD, 423 common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id)); 424 425 port->mac_control = 0; 426 if (!am65_cpsw_macsl_reset(port)) { 427 dev_err(dev, "mac_sl reset failed\n"); 428 ret = -EFAULT; 429 goto err_dis_rx; 430 } 431 432 if (priv->phydev->interface == PHY_INTERFACE_MODE_SGMII) { 433 writel(ADVERTISE_SGMII, 434 port->port_sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 435 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 436 port->port_sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 437 } 438 439 ret = phy_startup(priv->phydev); 440 if (ret) { 441 dev_err(dev, "phy_startup failed\n"); 442 goto err_dis_rx; 443 } 444 445 ret = am65_cpsw_update_link(priv); 446 if (!ret) { 447 ret = -ENODEV; 448 goto err_phy_shutdown; 449 } 450 451 common->started = true; 452 453 return 0; 454 455err_phy_shutdown: 456 phy_shutdown(priv->phydev); 457err_dis_rx: 458 /* disable ports */ 459 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id)); 460 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0)); 461 if (!am65_cpsw_macsl_wait_for_idle(port)) 462 dev_err(dev, "mac_sl idle timeout\n"); 463 writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG); 464 writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG); 465 writel(0, common->cpsw_base + AM65_CPSW_CTL_REG); 466 467 dma_disable(&common->dma_rx); 468err_dis_tx: 469 dma_disable(&common->dma_tx); 470err_free_rx: 471 dma_free(&common->dma_rx); 472err_free_tx: 473 dma_free(&common->dma_tx); 474err_off_clk: 475 clk_disable(&common->fclk); 476err_off_pwrdm: 477 power_domain_off(&common->pwrdmn); 478out: 479 dev_err(dev, "%s end error\n", __func__); 480 481 return ret; 482} 483 484static int am65_cpsw_send(struct udevice *dev, void *packet, int length) 485{ 486 struct am65_cpsw_priv *priv = dev_get_priv(dev); 487 struct am65_cpsw_common *common = priv->cpsw_common; 488 struct ti_udma_drv_packet_data packet_data; 489 int ret; 490 491 packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE; 492 packet_data.dest_tag = priv->port_id; 493 ret = dma_send(&common->dma_tx, packet, length, &packet_data); 494 if (ret) { 495 dev_err(dev, "TX dma_send failed %d\n", ret); 496 return ret; 497 } 498 499 return 0; 500} 501 502static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp) 503{ 504 struct am65_cpsw_priv *priv = dev_get_priv(dev); 505 struct am65_cpsw_common *common = priv->cpsw_common; 506 507 /* try to receive a new packet */ 508 return dma_receive(&common->dma_rx, (void **)packetp, NULL); 509} 510 511static int am65_cpsw_free_pkt(struct udevice *dev, uchar *packet, int length) 512{ 513 struct am65_cpsw_priv *priv = dev_get_priv(dev); 514 struct am65_cpsw_common *common = priv->cpsw_common; 515 int ret; 516 517 if (length > 0) { 518 u32 pkt = common->rx_next % UDMA_RX_DESC_NUM; 519 520 ret = dma_prepare_rcv_buf(&common->dma_rx, 521 net_rx_packets[pkt], 522 UDMA_RX_BUF_SIZE); 523 if (ret) 524 dev_err(dev, "RX dma free_pkt failed %d\n", ret); 525 common->rx_next++; 526 } 527 528 return 0; 529} 530 531static void am65_cpsw_stop(struct udevice *dev) 532{ 533 struct am65_cpsw_priv *priv = dev_get_priv(dev); 534 struct am65_cpsw_common *common = priv->cpsw_common; 535 struct am65_cpsw_port *port = &common->ports[priv->port_id]; 536 537 if (!common->started) 538 return; 539 540 phy_shutdown(priv->phydev); 541 542 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id)); 543 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0)); 544 if (!am65_cpsw_macsl_wait_for_idle(port)) 545 dev_err(dev, "mac_sl idle timeout\n"); 546 writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG); 547 writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG); 548 writel(0, common->cpsw_base + AM65_CPSW_CTL_REG); 549 550 dma_disable(&common->dma_tx); 551 dma_free(&common->dma_tx); 552 553 dma_disable(&common->dma_rx); 554 dma_free(&common->dma_rx); 555 556 common->started = false; 557} 558 559static int am65_cpsw_am654_get_efuse_macid(struct udevice *dev, 560 int slave, u8 *mac_addr) 561{ 562 u32 mac_lo, mac_hi, offset; 563 struct regmap *syscon; 564 int ret; 565 566 syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-efuse"); 567 if (IS_ERR(syscon)) { 568 if (PTR_ERR(syscon) == -ENODEV) 569 return 0; 570 return PTR_ERR(syscon); 571 } 572 573 ret = dev_read_u32_index(dev, "ti,syscon-efuse", 1, &offset); 574 if (ret) 575 return ret; 576 577 regmap_read(syscon, offset, &mac_lo); 578 regmap_read(syscon, offset + 4, &mac_hi); 579 580 mac_addr[0] = (mac_hi >> 8) & 0xff; 581 mac_addr[1] = mac_hi & 0xff; 582 mac_addr[2] = (mac_lo >> 24) & 0xff; 583 mac_addr[3] = (mac_lo >> 16) & 0xff; 584 mac_addr[4] = (mac_lo >> 8) & 0xff; 585 mac_addr[5] = mac_lo & 0xff; 586 587 return 0; 588} 589 590static int am65_cpsw_read_rom_hwaddr(struct udevice *dev) 591{ 592 struct am65_cpsw_priv *priv = dev_get_priv(dev); 593 struct eth_pdata *pdata = dev_get_plat(dev); 594 595 am65_cpsw_am654_get_efuse_macid(dev, 596 priv->port_id, 597 pdata->enetaddr); 598 599 return 0; 600} 601 602static const struct eth_ops am65_cpsw_ops = { 603 .start = am65_cpsw_start, 604 .send = am65_cpsw_send, 605 .recv = am65_cpsw_recv, 606 .free_pkt = am65_cpsw_free_pkt, 607 .stop = am65_cpsw_stop, 608 .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr, 609}; 610 611static int am65_cpsw_phy_init(struct udevice *dev) 612{ 613 struct am65_cpsw_priv *priv = dev_get_priv(dev); 614 struct eth_pdata *pdata = dev_get_plat(dev); 615 struct phy_device *phydev; 616 u32 supported = PHY_GBIT_FEATURES; 617 int ret; 618 619 phydev = dm_eth_phy_connect(dev); 620 if (!phydev) { 621 dev_err(dev, "phy_connect() failed\n"); 622 return -ENODEV; 623 } 624 625 phydev->supported &= supported; 626 if (pdata->max_speed) { 627 ret = phy_set_supported(phydev, pdata->max_speed); 628 if (ret) 629 return ret; 630 } 631 phydev->advertising = phydev->supported; 632 633 priv->phydev = phydev; 634 ret = phy_config(phydev); 635 if (ret < 0) 636 dev_err(dev, "phy_config() failed: %d", ret); 637 638 return ret; 639} 640 641static int am65_cpsw_ofdata_parse_phy(struct udevice *dev) 642{ 643 struct eth_pdata *pdata = dev_get_plat(dev); 644 struct am65_cpsw_priv *priv = dev_get_priv(dev); 645 646 dev_read_u32(dev, "reg", &priv->port_id); 647 648 pdata->phy_interface = dev_read_phy_mode(dev); 649 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { 650 dev_err(dev, "Invalid PHY mode, port %u\n", priv->port_id); 651 return -EINVAL; 652 } 653 654 dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed); 655 if (pdata->max_speed) 656 dev_err(dev, "Port %u speed froced to %uMbit\n", 657 priv->port_id, pdata->max_speed); 658 659 return 0; 660} 661 662static int am65_cpsw_port_probe(struct udevice *dev) 663{ 664 struct am65_cpsw_priv *priv = dev_get_priv(dev); 665 struct eth_pdata *pdata = dev_get_plat(dev); 666 struct am65_cpsw_common *cpsw_common; 667 char portname[32]; 668 int ret; 669 670 priv->dev = dev; 671 672 cpsw_common = dev_get_priv(dev->parent); 673 priv->cpsw_common = cpsw_common; 674 675 snprintf(portname, sizeof(portname), "%s%s", dev->parent->name, dev->name); 676 device_set_name(dev, portname); 677 678 ret = am65_cpsw_ofdata_parse_phy(dev); 679 if (ret) 680 goto out; 681 682 ret = am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface); 683 if (ret) 684 goto out; 685 686 ret = am65_cpsw_phy_init(dev); 687 688out: 689 return ret; 690} 691 692static int am65_cpsw_probe_nuss(struct udevice *dev) 693{ 694 struct am65_cpsw_common *cpsw_common = dev_get_priv(dev); 695 ofnode ports_np, node; 696 int ret, i; 697 struct udevice *port_dev; 698 699 cpsw_common->dev = dev; 700 cpsw_common->ss_base = dev_read_addr(dev); 701 if (cpsw_common->ss_base == FDT_ADDR_T_NONE) 702 return -EINVAL; 703 704 ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0); 705 if (ret) { 706 dev_err(dev, "failed to get pwrdmn: %d\n", ret); 707 return ret; 708 } 709 710 ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk); 711 if (ret) { 712 power_domain_free(&cpsw_common->pwrdmn); 713 dev_err(dev, "failed to get clock %d\n", ret); 714 return ret; 715 } 716 717 cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE; 718 cpsw_common->ale_base = cpsw_common->cpsw_base + 719 AM65_CPSW_CPSW_NU_ALE_BASE; 720 721 ports_np = dev_read_subnode(dev, "ethernet-ports"); 722 if (!ofnode_valid(ports_np)) { 723 ret = -ENOENT; 724 goto out; 725 } 726 727 ofnode_for_each_subnode(node, ports_np) { 728 const char *node_name; 729 u32 port_id; 730 bool disabled; 731 732 node_name = ofnode_get_name(node); 733 734 disabled = !ofnode_is_enabled(node); 735 736 ret = ofnode_read_u32(node, "reg", &port_id); 737 if (ret) { 738 dev_err(dev, "%s: failed to get port_id (%d)\n", 739 node_name, ret); 740 goto out; 741 } 742 743 if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) { 744 dev_err(dev, "%s: invalid port_id (%d)\n", 745 node_name, port_id); 746 ret = -EINVAL; 747 goto out; 748 } 749 cpsw_common->port_num++; 750 751 if (!port_id) 752 continue; 753 754 cpsw_common->ports[port_id].disabled = disabled; 755 if (disabled) 756 continue; 757 758 ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev); 759 if (ret) 760 dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node)); 761 } 762 763 for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) { 764 struct am65_cpsw_port *port = &cpsw_common->ports[i]; 765 766 port->port_base = cpsw_common->cpsw_base + 767 AM65_CPSW_CPSW_NU_PORTS_OFFSET + 768 (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET); 769 port->port_sgmii_base = cpsw_common->ss_base + 770 (i * AM65_CPSW_SGMII_BASE); 771 port->macsl_base = port->port_base + 772 AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET; 773 } 774 775 cpsw_common->bus_freq = 776 dev_read_u32_default(dev, "bus_freq", 777 AM65_CPSW_MDIO_BUS_FREQ_DEF); 778 779 dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u\n", 780 readl(cpsw_common->ss_base), 781 readl(cpsw_common->cpsw_base), 782 readl(cpsw_common->ale_base), 783 cpsw_common->port_num); 784 785out: 786 power_domain_free(&cpsw_common->pwrdmn); 787 return ret; 788} 789 790static const struct udevice_id am65_cpsw_nuss_ids[] = { 791 { .compatible = "ti,am654-cpsw-nuss" }, 792 { .compatible = "ti,j721e-cpsw-nuss" }, 793 { .compatible = "ti,am642-cpsw-nuss" }, 794 { } 795}; 796 797U_BOOT_DRIVER(am65_cpsw_nuss) = { 798 .name = "am65_cpsw_nuss", 799 .id = UCLASS_MISC, 800 .of_match = am65_cpsw_nuss_ids, 801 .probe = am65_cpsw_probe_nuss, 802 .priv_auto = sizeof(struct am65_cpsw_common), 803}; 804 805U_BOOT_DRIVER(am65_cpsw_nuss_port) = { 806 .name = "am65_cpsw_nuss_port", 807 .id = UCLASS_ETH, 808 .probe = am65_cpsw_port_probe, 809 .ops = &am65_cpsw_ops, 810 .priv_auto = sizeof(struct am65_cpsw_priv), 811 .plat_auto = sizeof(struct eth_pdata), 812 .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE, 813}; 814