Searched refs:pmc (Results 1 - 25 of 56) sorted by relevance

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/u-boot/arch/arm/mach-at91/
H A Dclock.c19 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
28 writel(id, &pmc->pcr);
30 div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV;
34 writel(regval, &pmc->pcr);
36 writel(0x01 << id, &pmc->pcer);
42 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
52 writel(regval, &pmc->pcr);
54 writel(0x01 << id, &pmc->pcdr);
60 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
62 writel(sys_clk, &pmc
67 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
74 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; local
95 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; local
113 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
120 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
[all...]
H A Dspl_atmel.c22 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
25 tmp = readl(&pmc->mor);
31 writel(tmp, &pmc->mor);
32 while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS))
37 tmp = readl(&pmc->mcfr);
40 writel(tmp, &pmc->mcfr);
42 while (!(readl(&pmc->mcfr) & AT91_PMC_MCFR_MAINRDY))
45 if (!(readl(&pmc->mcfr) & AT91_PMC_MCFR_MAINF_MASK))
49 tmp = readl(&pmc->mor);
61 writel(tmp, &pmc
[all...]
H A Dspl_at91.c36 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
38 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
40 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
43 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
48 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
51 tmp = readl(&pmc->mckr);
54 writel(tmp, &pmc->mckr);
55 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
60 writel(tmp, &pmc->mckr);
61 while (!(readl(&pmc
[all...]
/u-boot/arch/arm/mach-tegra/
H A Dsys_info.c11 #include <asm/arch-tegra/pmc.h>
15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
17 switch (pmc->pmc_reset_status) {
H A Dcmd_enterrcm.c32 #include <asm/arch-tegra/pmc.h>
/u-boot/arch/x86/include/asm/arch-apollolake/
H A Dcpu.h29 * @pmc: PMC device
31 void enable_pm_timer_emulation(const struct udevice *pmc);
/u-boot/arch/arm/mach-tegra/tegra20/
H A Dcpu.c9 #include <asm/arch-tegra/pmc.h>
15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
18 reg = readl(&pmc->pmc_cntrl);
20 writel(reg, &pmc->pmc_cntrl);
H A Dwarmboot_avp.c16 #include <asm/arch-tegra/pmc.h>
26 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
67 if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) {
69 writel(reg, &pmc->pmc_pwrgate_toggle);
70 while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU))
75 reg = readl(&pmc->pmc_remove_clamping);
77 writel(reg, &pmc->pmc_remove_clamping);
99 reg = readl(&pmc->pmc_scratch41);
142 writel(reg, &pmc->pmc_scratch1);
146 scratch3.word = readl(&pmc
[all...]
/u-boot/drivers/power/acpi_pmc/
H A DMakefile5 obj-y += acpi-pmc-uclass.o
/u-boot/arch/arm/mach-at91/armv7/
H A Dclock.c60 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
71 tmp = readl(&pmc->mcfr);
80 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
86 mckr = readl(&pmc->mckr);
119 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
121 writel(pllar, &pmc->pllar);
122 while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
128 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
131 tmp = readl(&pmc->mckr);
148 writel(tmp, &pmc
162 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
198 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
261 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
[all...]
/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dclock.c117 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; local
128 tmp = readl(&pmc->mcfr);
137 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
156 mckr = readl(&pmc->mckr);
205 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
207 writel(pllar, &pmc->pllar);
208 while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
213 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
215 writel(pllbr, &pmc->pllbr);
216 while (!(readl(&pmc
222 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
256 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; local
274 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; local
[all...]
/u-boot/arch/arm/mach-tegra/tegra124/
H A Dcpu.c16 #include <asm/arch-tegra/pmc.h>
29 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
43 writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
46 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
47 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
157 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
174 val = readl(&pmc->pmc_osc_edpd_over);
177 writel(val, &pmc->pmc_osc_edpd_over);
180 setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
239 struct pmc_ctlr *pmc local
249 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
288 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
328 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
[all...]
H A DMakefile11 obj-y += pmc.o
/u-boot/arch/arm/include/asm/arch-stm32f7/
H A Dsyscfg.h16 u32 pmc; member in struct:stm32_syscfg_regs
/u-boot/arch/arm/mach-at91/arm920t/
H A Dclock.c109 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; local
120 tmp = readl(&pmc->mcfr);
129 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
148 mckr = readl(&pmc->mckr);
163 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; local
167 writel(pllbr, &pmc->pllbr);
168 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
181 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; local
185 writel(0, &pmc->pllbr);
186 while ((readl(&pmc
[all...]
/u-boot/arch/x86/cpu/apollolake/
H A Dcpu_spl.c97 struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc; local
100 ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
105 ret = pmc_global_reset_set_enable(pmc, false);
109 enable_pm_timer_emulation(pmc);
133 ret = pmc_disable_tco(pmc);
136 ret = pmc_gpe_init(pmc);
156 struct udevice *pmc, *p2sb; local
159 ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
170 ret = pmc_init(pmc);
174 ret = pmc_prev_sleep_state(pmc);
[all...]
H A Dpmc.c6 * Modified from coreboot pmclib.c, pmc.c and pmutil.c
19 #include <asm/arch/pmc.h>
131 /* Get the dwX values for pmc gpe settings */
167 pci_dev_t pmc = priv->bdf; local
173 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_0, (ulong)upriv->pmc_bar0,
175 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
176 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_2, (ulong)upriv->pmc_bar2,
178 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_3, 0, PCI_SIZE_32);
179 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_4, upriv->acpi_base,
181 pci_x86_write_config(pmc, PCI_COMMAN
[all...]
/u-boot/arch/arm/mach-tegra/tegra30/
H A Dcpu.c13 #include <asm/arch-tegra/pmc.h>
23 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
27 reg = readl(&pmc->pmc_cntrl);
29 writel(reg, &pmc->pmc_cntrl);
/u-boot/arch/arm/mach-tegra/tegra114/
H A Dcpu.c15 #include <asm/arch-tegra/pmc.h>
26 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
41 writel(reg, &pmc->pmc_cpupwrgood_timer);
44 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
45 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
194 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
198 reg = readl(&pmc->pmc_pwrgate_status);
204 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; local
208 reg = readl(&pmc->pmc_clamp_status);
214 struct pmc_ctlr *pmc local
[all...]
/u-boot/arch/x86/include/asm/
H A Ditss.h56 u32 pmc; member in struct:pmc_route
/u-boot/drivers/sysreset/
H A Dsysreset_tegra.c10 #include <asm/arch-tegra/pmc.h>
/u-boot/drivers/clk/at91/
H A Dcompat.c21 #include "pmc.h"
31 { .compatible = "atmel,at91rm9200-pmc" },
32 { .compatible = "atmel,at91sam9260-pmc" },
33 { .compatible = "atmel,at91sam9g45-pmc" },
34 { .compatible = "atmel,at91sam9n12-pmc" },
35 { .compatible = "atmel,at91sam9x5-pmc" },
36 { .compatible = "atmel,sama5d3-pmc" },
37 { .compatible = "atmel,sama5d2-pmc" },
42 .name = "at91-pmc",
200 struct at91_pmc *pmc local
241 struct at91_pmc *pmc = plat->reg_base; local
287 struct at91_pmc *pmc = plat->reg_base; local
306 struct at91_pmc *pmc = plat->reg_base; local
410 struct at91_pmc *pmc = plat->reg_base; local
492 struct at91_pmc *pmc = plat->reg_base; local
556 struct at91_pmc *pmc = plat->reg_base; local
685 struct at91_pmc *pmc = plat->reg_base; local
758 struct at91_pmc *pmc = plat->reg_base; local
781 struct at91_pmc *pmc = plat->reg_base; local
894 struct at91_pmc *pmc = plat->reg_base; local
915 struct at91_pmc *pmc = plat->reg_base; local
[all...]
H A DMakefile6 obj-y += pmc.o sckc.o clk-main.o clk-master.o clk-programmable.o clk-system.o
/u-boot/board/atmel/sama5d2_xplained/
H A Dsama5d2_xplained.c152 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
160 writel(AT91_PMC_DDR, &pmc->scer);
180 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
199 writel(0x0 << 8, &pmc->pllicpr);
/u-boot/arch/arm/mach-at91/include/mach/
H A Dclk.h63 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; local
65 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;

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