1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2010-2014 4 * NVIDIA Corporation <www.nvidia.com> 5 */ 6 7#include <common.h> 8#include <log.h> 9#include <asm/io.h> 10#include <asm/arch/clock.h> 11#include <asm/arch/flow.h> 12#include <asm/arch/pinmux.h> 13#include <asm/arch/tegra.h> 14#include <asm/arch-tegra/clk_rst.h> 15#include <asm/arch-tegra/pmc.h> 16#include <asm/arch-tegra/tegra_i2c.h> 17#include <linux/delay.h> 18#include "../cpu.h" 19 20/* In case this function is not defined */ 21__weak void pmic_enable_cpu_vdd(void) {} 22 23/* Tegra114-specific CPU init code */ 24static void enable_cpu_power_rail(void) 25{ 26 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 27 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 28 u32 reg; 29 30 debug("%s entry\n", __func__); 31 32 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ 33 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); 34 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); 35 36 /* 37 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), 38 * set it for 25ms (102MHz * .025) 39 */ 40 reg = 0x26E8F0; 41 writel(reg, &pmc->pmc_cpupwrgood_timer); 42 43 /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */ 44 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); 45 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); 46 47 /* 48 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH 49 * to 408 to satisfy the requirement of having at least 16 CPU clock 50 * cycles before clamp removal. 51 */ 52 53 clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF); 54 setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408); 55} 56 57static void enable_cpu_clocks(void) 58{ 59 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 60 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; 61 u32 reg; 62 63 debug("%s entry\n", __func__); 64 65 /* Wait for PLL-X to lock */ 66 do { 67 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); 68 } while ((reg & (1 << pllinfo->lock_det)) == 0); 69 70 /* Wait until all clocks are stable */ 71 udelay(PLL_STABILIZATION_DELAY); 72 73 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); 74 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); 75 76 /* Always enable the main CPU complex clocks */ 77 clock_enable(PERIPH_ID_CPU); 78 clock_enable(PERIPH_ID_CPULP); 79 clock_enable(PERIPH_ID_CPUG); 80} 81 82static void remove_cpu_resets(void) 83{ 84 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 85 u32 reg; 86 87 debug("%s entry\n", __func__); 88 /* Take the slow non-CPU partition out of reset */ 89 reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr); 90 writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr); 91 92 /* Take the fast non-CPU partition out of reset */ 93 reg = readl(&clkrst->crc_rst_cpug_cmplx_clr); 94 writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr); 95 96 /* Clear the SW-controlled reset of the slow cluster */ 97 reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr); 98 reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0); 99 writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr); 100 101 /* Clear the SW-controlled reset of the fast cluster */ 102 reg = readl(&clkrst->crc_rst_cpug_cmplx_clr); 103 reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0); 104 reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1); 105 reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2); 106 reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3); 107 writel(reg, &clkrst->crc_rst_cpug_cmplx_clr); 108} 109 110/** 111 * Tegra114 requires some special clock initialization, including setting up 112 * the DVC I2C, turning on MSELECT and selecting the G CPU cluster 113 */ 114void t114_init_clocks(void) 115{ 116 struct clk_rst_ctlr *clkrst = 117 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; 118 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; 119 u32 val; 120 121 debug("%s entry\n", __func__); 122 123 /* Set active CPU cluster to G */ 124 clrbits_le32(&flow->cluster_control, 1); 125 126 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div); 127 128 debug("Setting up PLLX\n"); 129 init_pllx(); 130 131 val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); 132 writel(val, &clkrst->crc_clk_sys_rate); 133 134 /* Enable clocks to required peripherals. TBD - minimize this list */ 135 debug("Enabling clocks\n"); 136 137 clock_set_enable(PERIPH_ID_CACHE2, 1); 138 clock_set_enable(PERIPH_ID_GPIO, 1); 139 clock_set_enable(PERIPH_ID_TMR, 1); 140 clock_set_enable(PERIPH_ID_RTC, 1); 141 clock_set_enable(PERIPH_ID_CPU, 1); 142 clock_set_enable(PERIPH_ID_EMC, 1); 143 clock_set_enable(PERIPH_ID_I2C5, 1); 144 clock_set_enable(PERIPH_ID_FUSE, 1); 145 clock_set_enable(PERIPH_ID_PMC, 1); 146 clock_set_enable(PERIPH_ID_APBDMA, 1); 147 clock_set_enable(PERIPH_ID_MEM, 1); 148 clock_set_enable(PERIPH_ID_IRAMA, 1); 149 clock_set_enable(PERIPH_ID_IRAMB, 1); 150 clock_set_enable(PERIPH_ID_IRAMC, 1); 151 clock_set_enable(PERIPH_ID_IRAMD, 1); 152 clock_set_enable(PERIPH_ID_CORESIGHT, 1); 153 clock_set_enable(PERIPH_ID_MSELECT, 1); 154 clock_set_enable(PERIPH_ID_EMC1, 1); 155 clock_set_enable(PERIPH_ID_MC1, 1); 156 clock_set_enable(PERIPH_ID_DVFS, 1); 157 158 /* 159 * Set MSELECT clock source as PLLP (00), and ask for a clock 160 * divider that would set the MSELECT clock at 102MHz for a 161 * PLLP base of 408MHz. 162 */ 163 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 164 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); 165 166 /* I2C5 (DVC) gets CLK_M and a divisor of 17 */ 167 clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16); 168 169 /* Give clocks time to stabilize */ 170 udelay(1000); 171 172 /* Take required peripherals out of reset */ 173 debug("Taking periphs out of reset\n"); 174 reset_set_enable(PERIPH_ID_CACHE2, 0); 175 reset_set_enable(PERIPH_ID_GPIO, 0); 176 reset_set_enable(PERIPH_ID_TMR, 0); 177 reset_set_enable(PERIPH_ID_COP, 0); 178 reset_set_enable(PERIPH_ID_EMC, 0); 179 reset_set_enable(PERIPH_ID_I2C5, 0); 180 reset_set_enable(PERIPH_ID_FUSE, 0); 181 reset_set_enable(PERIPH_ID_APBDMA, 0); 182 reset_set_enable(PERIPH_ID_MEM, 0); 183 reset_set_enable(PERIPH_ID_CORESIGHT, 0); 184 reset_set_enable(PERIPH_ID_MSELECT, 0); 185 reset_set_enable(PERIPH_ID_EMC1, 0); 186 reset_set_enable(PERIPH_ID_MC1, 0); 187 reset_set_enable(PERIPH_ID_DVFS, 0); 188 189 debug("%s exit\n", __func__); 190} 191 192static bool is_partition_powered(u32 partid) 193{ 194 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 195 u32 reg; 196 197 /* Get power gate status */ 198 reg = readl(&pmc->pmc_pwrgate_status); 199 return !!(reg & (1 << partid)); 200} 201 202static bool is_clamp_enabled(u32 partid) 203{ 204 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 205 u32 reg; 206 207 /* Get clamp status. */ 208 reg = readl(&pmc->pmc_clamp_status); 209 return !!(reg & (1 << partid)); 210} 211 212static void power_partition(u32 partid) 213{ 214 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; 215 216 debug("%s: part ID = %08X\n", __func__, partid); 217 /* Is the partition already on? */ 218 if (!is_partition_powered(partid)) { 219 /* No, toggle the partition power state (OFF -> ON) */ 220 debug("power_partition, toggling state\n"); 221 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); 222 223 /* Wait for the power to come up */ 224 while (!is_partition_powered(partid)) 225 ; 226 227 /* Wait for the clamp status to be cleared */ 228 while (is_clamp_enabled(partid)) 229 ; 230 231 /* Give I/O signals time to stabilize */ 232 udelay(IO_STABILIZATION_DELAY); 233 } 234} 235 236void powerup_cpus(void) 237{ 238 /* We boot to the fast cluster */ 239 debug("%s entry: G cluster\n", __func__); 240 241 /* Power up the fast cluster rail partition */ 242 power_partition(CRAIL); 243 244 /* Power up the fast cluster non-CPU partition */ 245 power_partition(C0NC); 246 247 /* Power up the fast cluster CPU0 partition */ 248 power_partition(CE0); 249} 250 251void start_cpu(u32 reset_vector) 252{ 253 u32 imme, inst; 254 255 debug("%s entry, reset_vector = %x\n", __func__, reset_vector); 256 257 t114_init_clocks(); 258 259 /* Enable VDD_CPU */ 260 enable_cpu_power_rail(); 261 pmic_enable_cpu_vdd(); 262 263 /* Get the CPU(s) running */ 264 enable_cpu_clocks(); 265 266 /* Enable CoreSight */ 267 clock_enable_coresight(1); 268 269 /* Take CPU(s) out of reset */ 270 remove_cpu_resets(); 271 272 /* Set the entry point for CPU execution from reset */ 273 274 /* 275 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc. 276 * See nvbug 1193357 for details. 277 */ 278 279 /* mov r0, #lsb(reset_vector) */ 280 imme = reset_vector & 0xffff; 281 inst = imme & 0xfff; 282 inst |= ((imme >> 12) << 16); 283 inst |= 0xe3000000; 284 writel(inst, 0x4003fff0); 285 286 /* movt r0, #msb(reset_vector) */ 287 imme = (reset_vector >> 16) & 0xffff; 288 inst = imme & 0xfff; 289 inst |= ((imme >> 12) << 16); 290 inst |= 0xe3400000; 291 writel(inst, 0x4003fff4); 292 293 /* bx r0 */ 294 writel(0xe12fff10, 0x4003fff8); 295 296 /* b -12 */ 297 imme = (u32)-20; 298 inst = (imme >> 2) & 0xffffff; 299 inst |= 0xea000000; 300 writel(inst, 0x4003fffc); 301 302 /* Write to original location for compatibility */ 303 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); 304 305 /* If the CPU(s) don't already have power, power 'em up */ 306 powerup_cpus(); 307} 308