Searched refs:pe (Results 1 - 21 of 21) sorted by relevance

/u-boot/fs/btrfs/
H A Dextent-cache.h29 struct cache_extent *prev_cache_extent(struct cache_extent *pe);
30 struct cache_extent *next_cache_extent(struct cache_extent *pe);
57 int insert_cache_extent(struct cache_tree *tree, struct cache_extent *pe);
58 void remove_cache_extent(struct cache_tree *tree, struct cache_extent *pe);
65 typedef void (*free_cache_extent)(struct cache_extent *pe);
93 int insert_cache_extent2(struct cache_tree *tree, struct cache_extent *pe);
H A Dextent-cache.c90 struct cache_extent *pe = malloc(sizeof(*pe)); local
92 if (!pe)
93 return pe;
95 pe->objectid = 0;
96 pe->start = start;
97 pe->size = size;
98 return pe;
103 struct cache_extent *pe = alloc_cache_extent(start, size); local
106 if (!pe)
116 insert_cache_extent(struct cache_tree *tree, struct cache_extent *pe) argument
121 insert_cache_extent2(struct cache_tree *tree, struct cache_extent *pe) argument
219 prev_cache_extent(struct cache_extent *pe) argument
228 next_cache_extent(struct cache_extent *pe) argument
237 remove_cache_extent(struct cache_tree *tree, struct cache_extent *pe) argument
253 free_extent_cache(struct cache_extent *pe) argument
[all...]
/u-boot/drivers/net/
H A Dmvpp2.c1393 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) argument
1397 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1401 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1404 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1406 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1409 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1411 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1417 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) argument
1421 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1425 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe
1468 mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) argument
1477 mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, unsigned int port, bool add) argument
1489 mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, unsigned int ports) argument
1501 mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) argument
1509 mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, unsigned int offs, unsigned char byte, unsigned char enable) argument
1518 mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, unsigned int offs, unsigned char *byte, unsigned char *enable) argument
1527 mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, unsigned short ethertype) argument
1535 mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, int val) argument
1542 mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, int val) argument
1549 mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, unsigned int bits, unsigned int mask) argument
1570 mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, unsigned int bits, unsigned int mask) argument
1591 mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) argument
1607 mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) argument
1620 mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, unsigned int op) argument
1647 mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, unsigned int type, int offset, unsigned int op) argument
1696 struct mvpp2_prs_entry *pe; local
1748 struct mvpp2_prs_entry pe; local
1783 struct mvpp2_prs_entry pe; local
1825 struct mvpp2_prs_entry pe; local
1900 struct mvpp2_prs_entry pe; local
1924 struct mvpp2_prs_entry pe; local
1947 struct mvpp2_prs_entry pe; local
1977 struct mvpp2_prs_entry pe; local
2244 mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, const u8 *da, unsigned char *mask) argument
2267 struct mvpp2_prs_entry *pe; local
2302 struct mvpp2_prs_entry *pe; local
2412 struct mvpp2_prs_entry *pe; local
[all...]
/u-boot/drivers/net/pfe_eth/
H A Dpfe_hw.c11 static struct pe_info pe[MAX_PE]; variable in typeref:struct:pe_info
22 pe[pfe_pe_id].dmem_base_addr =
24 pe[pfe_pe_id].pmem_base_addr =
26 pe[pfe_pe_id].pmem_size = (u32)CLASS_IMEM_SIZE;
27 pe[pfe_pe_id].mem_access_wdata =
29 pe[pfe_pe_id].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
30 pe[pfe_pe_id].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
36 pe[pfe_pe_id].dmem_base_addr =
38 pe[pfe_pe_id].pmem_base_addr =
40 pe[pfe_pe_i
[all...]
/u-boot/drivers/video/tegra124/
H A Ddp.c864 static int tegra_dp_lt_adjust(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], argument
878 pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >>
882 pe[1 + 2 * cnt] =
1007 static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], argument
1043 pe_reg = tegra_dp_pe_regs[pc[cnt]][vs[cnt]][pe[cnt]];
1044 vs_reg = tegra_dp_vs_regs[pc[cnt]][vs[cnt]][pe[cnt]];
1045 pc_reg = tegra_dp_pc_regs[pc[cnt]][vs[cnt]][pe[cnt]];
1056 u32 max_vs_flag = tegra_dp_is_max_vs(pe[cnt], vs[cnt]);
1057 u32 max_pe_flag = tegra_dp_is_max_pe(pe[cnt], vs[cnt]);
1063 (pe[cn
1092 _tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], u32 pc[4], u8 pc_supported, u32 n_lanes, const struct tegra_dp_link_config *cfg) argument
1124 tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], u32 pc[4], const struct tegra_dp_link_config *cfg) argument
1145 _tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], u32 pc[4], u8 pc_supported, u32 n_lanes, const struct tegra_dp_link_config *cfg) argument
1172 tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], u32 pc[4], const struct tegra_dp_link_config *cfg) argument
1196 u32 pe[4], vs[4], pc[4]; local
[all...]
H A Ddisplayport.h292 static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) argument
294 return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1;
297 static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) argument
299 return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1;
/u-boot/scripts/
H A Dspdxcheck.py197 except ParserException as pe:
198 if pe.tok:
199 col = line.find(expr) + pe.tok.lexpos
200 tok = pe.tok.value
201 sys.stdout.write('%s: %d:%d %s: %s\n' %(fname, self.curline, col, pe.txt, tok))
203 sys.stdout.write('%s: %d:0 %s\n' %(fname, self.curline, col, pe.txt))
/u-boot/arch/arm/lib/
H A Dcrt0_arm_efi.S10 #include <asm-generic/pe.h>
H A Dcrt0_aarch64_efi.S11 #include <asm-generic/pe.h>
/u-boot/arch/riscv/lib/
H A Dcrt0_riscv_efi.S11 #include <asm-generic/pe.h>
/u-boot/include/
H A Dpe.h13 #include <asm-generic/pe.h>
H A Defi_loader.h17 #include <pe.h>
594 /* measure the pe-coff image, extend PCR and add Event Log */
H A Defi_api.h21 #include <pe.h>
/u-boot/lib/rsa/
H A Drsa-sign.c328 static int rsa_engine_init(const char *engine_id, ENGINE **pe) argument
364 *pe = e;
/u-boot/arch/arm/mach-imx/imx9/
H A Dtrdc.c77 u8 did, u8 pe, u8 pidm, u8 pid)
87 ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) |
76 trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids, u8 did, u8 pe, u8 pidm, u8 pid) argument
/u-boot/drivers/video/zynqmp/
H A Dzynqmp_dpsub.h657 static const u32 pe[4][4] = { variable
H A Dzynqmp_dpsub.c961 writel(pe[pe_level_rx][vs_level_rx], (ulong)SERDES_BASEADDR +
/u-boot/lib/efi_loader/
H A Defi_image_loader.c16 #include <pe.h>
H A Defi_boottime.c16 #include <pe.h>
/u-boot/tools/
H A Dmkeficapsule.c8 #include <pe.h>
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-pciercx-defs.h4290 u32 pe : 1; member in struct:cvmx_pciercx_cfg087::cvmx_pciercx_cfg087_s

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