1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2023, Advanced Micro Devices, Inc. 4 * 5 */ 6 7#ifndef _VIDEO_ZYNQMP_DPSUB_H 8#define _VIDEO_ZYNQMP_DPSUB_H 9 10enum video_mode { 11 VIDC_VM_640x480_60_P = 0, 12 VIDC_VM_1024x768_60_P = 1, 13}; 14 15enum { 16 LANE_COUNT_1 = 1, 17 LANE_COUNT_2 = 2, 18}; 19 20enum { 21 LINK_RATE_162GBPS = 0x06, 22 LINK_RATE_270GBPS = 0x0A, 23 LINK_RATE_540GBPS = 0x14, 24}; 25 26enum video_color_depth { 27 VIDC_BPC_6 = 6, 28 VIDC_BPC_8 = 8, 29 VIDC_BPC_10 = 10, 30 VIDC_BPC_12 = 12, 31 VIDC_BPC_14 = 14, 32 VIDC_BPC_16 = 16, 33 VIDC_BPC_NUM_SUPPORTED = 6, 34 VIDC_BPC_UNKNOWN 35}; 36 37enum video_color_encoding { 38 DP_CENC_RGB = 0, 39 DP_CENC_YONLY, 40}; 41 42enum dp_dma_channel_type { 43 VIDEO_CHAN, 44 GRAPHICS_CHAN, 45}; 46 47enum dp_dma_channel_state { 48 DPDMA_DISABLE, 49 DPDMA_ENABLE, 50 DPDMA_IDLE, 51 DPDMA_PAUSE 52}; 53 54enum link_training_states { 55 TS_CLOCK_RECOVERY, 56 TS_CHANNEL_EQUALIZATION, 57 TS_ADJUST_LINK_RATE, 58 TS_ADJUST_LANE_COUNT, 59 TS_FAILURE, 60 TS_SUCCESS 61}; 62 63enum video_frame_rate { 64 VIDC_FR_60HZ = 60, 65 VIDC_FR_NUM_SUPPORTED = 2, 66 VIDC_FR_UNKNOWN 67}; 68 69enum av_buf_video_modes { 70 INTERLEAVED, 71 SEMIPLANAR 72}; 73 74enum av_buf_video_format { 75 RGBA8888 = 1, 76}; 77 78enum av_buf_video_stream { 79 AVBUF_VIDSTREAM1_LIVE, 80 AVBUF_VIDSTREAM1_NONLIVE, 81 AVBUF_VIDSTREAM1_TPG, 82 AVBUF_VIDSTREAM1_NONE, 83}; 84 85enum av_buf_gfx_stream { 86 AVBUF_VIDSTREAM2_DISABLEGFX = 0x0, 87 AVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4, 88 AVBUF_VIDSTREAM2_LIVE_GFX = 0x8, 89 AVBUF_VIDSTREAM2_NONE = 0xC0, 90}; 91 92/** 93 * struct aux_transaction - Description of an AUX channel transaction 94 * @cmd_code: Command code of the transaction 95 * @num_bytes: The number of bytes in the transaction's payload data 96 * @address: The DPCD address of the transaction 97 * @data: Payload data of the AUX channel transaction 98 */ 99struct aux_transaction { 100 u16 cmd_code; 101 u8 num_bytes; 102 u32 address; 103 u8 *data; 104}; 105 106/** 107 * struct link_config - Description of link configuration 108 * @lane_count: Currently selected lane count for this link 109 * @link_rate: Currently selected link rate for this link 110 * @scrambler_en: Flag to determine whether the scrambler is 111 * enabled for this link 112 * @enhanced_framing_mode: Flag to determine whether enhanced framing 113 * mode is active for this link 114 * @max_lane_count: Maximum lane count for this link 115 * @max_link_rate: Maximum link rate for this link 116 * @support_enhanced_framing_mode: Flag to indicate whether the link supports 117 * enhanced framing mode 118 * @vs_level: Voltage swing for each lane 119 * @pe_level: Pre-emphasis/cursor level for each lane 120 * @pattern: The current pattern currently in use over the main link 121 */ 122struct link_config { 123 u8 lane_count; 124 u8 link_rate; 125 u8 scrambler_en; 126 u8 enhanced_framing_mode; 127 u8 max_lane_count; 128 u8 max_link_rate; 129 u8 support_enhanced_framing_mode; 130 u8 support_downspread_control; 131 u8 vs_level; 132 u8 pe_level; 133 u8 pattern; 134}; 135 136struct video_timing { 137 u16 h_active; 138 u16 h_front_porch; 139 u16 h_sync_width; 140 u16 h_back_porch; 141 u16 h_total; 142 bool h_sync_polarity; 143 u16 v_active; 144 u16 f0_pv_front_porch; 145 u16 f0_pv_sync_width; 146 u16 f0_pv_back_porch; 147 u16 f0_pv_total; 148 u16 f1_v_front_porch; 149 u16 f1_v_sync_width; 150 u16 f1_v_back_porch; 151 u16 f1_v_total; 152 bool v_sync_polarity; 153}; 154 155struct video_timing_mode { 156 enum video_mode vid_mode; 157 char name[21]; 158 enum video_frame_rate frame_rate; 159 struct video_timing video_timing; 160}; 161 162/* 163 * struct main_stream_attributes - Main Stream Attributes (MSA) 164 * @pixel_clock_hz: The pixel clock of the stream (in Hz) 165 * @h_start: Horizontal blank start (in pixels) 166 * @v_start: Vertical blank start (in lines). 167 * @misc0: Miscellaneous stream attributes 0 168 * @misc1: Miscellaneous stream attributes 1 169 * @n_vid N value for the video stream 170 * @user_pixel_width: The width of the user data input port. 171 * @data_per_plane: Used to translate the number of pixels per 172 * line to the native internal 16-bit datapath. 173 * @avg_bytes_per_tu: Average number of bytes per transfer unit, 174 * scaled up by a factor of 1000. 175 * @transfer_unit_size: Size of the transfer unit in the 176 * framing logic. 177 * @init_wait: Number of initial wait cycles at the start 178 * of a new line by the framing logic. 179 * @bits_per_color: Number of bits per color component. 180 * @component_format: The component format currently in 181 * use by the video stream. 182 * @dynamic_range: The dynamic range currently in use 183 * by the video stream. 184 * @y_cb_cr_colorimetry: The YCbCr colorimetry currently in 185 * use by the video stream. 186 * @synchronous_clock_mode: Synchronous clock mode is currently 187 * in use by the video stream. 188 */ 189struct main_stream_attributes { 190 struct video_timing_mode vid_timing_mode; 191 u32 pixel_clock_hz; 192 u32 h_start; 193 u32 v_start; 194 u32 misc0; 195 u32 misc1; 196 u32 n_vid; 197 u32 user_pixel_width; 198 u32 data_per_lane; 199 u32 avg_bytes_per_tu; 200 u32 transfer_unit_size; 201 u32 init_wait; 202 u32 bits_per_color; 203 u8 component_format; 204 u8 dynamic_range; 205 u8 y_cb_cr_colorimetry; 206 u8 synchronous_clock_mode; 207}; 208 209struct av_buf_vid_attribute { 210 enum av_buf_video_format video_format; 211 u8 value; 212 enum av_buf_video_modes mode; 213 u32 sf[3]; 214 u8 sampling_en; 215 u8 is_rgb; 216 u8 swap; 217 u8 bpp; 218}; 219 220struct av_buf_mode { 221 enum av_buf_video_stream video_src; 222 enum av_buf_gfx_stream gfx_src; 223 u8 video_clk; 224}; 225 226struct dp_dma_descriptor { 227 u32 control; 228 u32 dscr_id; 229 u32 xfer_size; 230 u32 line_size_stride; 231 u32 lsb_timestamp; 232 u32 msb_timestamp; 233 u32 addr_ext; 234 u32 next_desr; 235 u32 src_addr; 236 u32 addr_ext_23; 237 u32 addr_ext_45; 238 u32 src_addr2; 239 u32 src_addr3; 240 u32 src_addr4; 241 u32 src_addr5; 242 u32 crc; 243}; 244 245struct dp_dma_channel { 246 struct dp_dma_descriptor *cur; 247}; 248 249struct dp_dma_frame_buffer { 250 u64 address; 251 u32 size; 252 u32 stride; 253 u32 line_size; 254}; 255 256struct dp_dma_gfx_channel { 257 struct dp_dma_channel channel; 258 u8 trigger_status; 259 u8 av_buf_en; 260 struct dp_dma_frame_buffer *frame_buffer; 261}; 262 263struct dp_dma { 264 phys_addr_t base_addr; 265 struct dp_dma_gfx_channel gfx; 266}; 267 268/** 269 * struct zynqmp_dpsub_priv - Private structure 270 * @dev: Device uclass for video_ops 271 */ 272struct zynqmp_dpsub_priv { 273 phys_addr_t base_addr; 274 u32 clock; 275 struct av_buf_vid_attribute *non_live_graphics; 276 struct av_buf_mode av_mode; 277 struct dp_dma_frame_buffer frame_buffer; 278 279 struct link_config link_config; 280 struct main_stream_attributes msa_config; 281 struct dp_dma *dp_dma; 282 enum video_mode video_mode; 283 enum video_color_depth bpc; 284 enum video_color_encoding color_encode; 285 u32 pix_clk; 286 u8 dpcd_rx_caps[16]; 287 u8 lane_status_ajd_reqs[6]; 288 u8 sink_count; 289 u8 use_max_lane_count; 290 u8 use_max_link_rate; 291 u8 lane_count; 292 u8 link_rate; 293 u8 use_max_cfg_caps; 294 u8 en_sync_clk_mode; 295}; 296 297/**************************** Variable Definitions ****************************/ 298#define TRAINING_PATTERN_SET 0x000C 299#define TRAINING_PATTERN_SET_OFF 0x0 300#define SCRAMBLING_DISABLE 0x0014 301#define TRAINING_PATTERN_SET_TP1 0x1 302#define TRAINING_PATTERN_SET_TP2 0x2 303#define TRAINING_PATTERN_SET_TP3 0x3 304 305#define AVBUF_BUF_4BIT_SF 0x11111 306#define AVBUF_BUF_5BIT_SF 0x10842 307#define AVBUF_BUF_6BIT_SF 0x10410 308#define AVBUF_BUF_8BIT_SF 0x10101 309#define AVBUF_BUF_10BIT_SF 0x10040 310#define AVBUF_BUF_12BIT_SF 0x10000 311#define AVBUF_BUF_6BPC 0x000 312#define AVBUF_BUF_8BPC 0x001 313#define AVBUF_BUF_10BPC 0x010 314#define AVBUF_BUF_12BPC 0x011 315#define AVBUF_CHBUF3 0x0000B01C 316#define AVBUF_CHBUF3_BURST_LEN_SHIFT 2 317#define AVBUF_CHBUF3_FLUSH_MASK 0x00000002 318#define AVBUF_CHBUF0_EN_MASK 0x00000001 319#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT 0x0000B070 320#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK 0x0000000C 321#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK 0x00000003 322#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT 0x0000B070 323#define AVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0x0000B200 324#define AVBUF_V_BLEND_LAYER1_CONTROL 0x0000A01C 325#define AVBUF_V_BLEND_IN2CSC_COEFF0 0x0000A080 326#define AVBUF_BUF_FORMAT 0x0000B000 327#define AVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK 0x0000001F 328#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK 0x00000F00 329#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT 8 330#define AVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT 1 331#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT 4 332#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT 0x0000A014 333#define AVBUF_V_BLEND_RGB2YCBCR_COEFF0 0x0000A020 334#define AVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0x0000A074 335#define AVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 336#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT 1 337#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0x0000A00C 338#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT 1 339#define DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT 3 340#define DP_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT 4 341#define DP_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK 0x00000080 342#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422 0x1 343#define AVBUF_PL_CLK 0x0 344#define AVBUF_PS_CLK 0x1 345#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT 2 346#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0 347#define AVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT 1 348#define AVBUF_BUF_AUD_VID_CLK_SOURCE 0x0000B120 349#define AVBUF_BUF_SRST_REG 0x0000B124 350#define AVBUF_BUF_SRST_REG_VID_RST_MASK 0x00000002 351#define AVBUF_CLK_FPD_BASEADDR 0xFD1A0000 352#define AVBUF_CLK_LPD_BASEADDR 0xFF5E0000 353#define AVBUF_LPD_CTRL_OFFSET 16 354#define AVBUF_FPD_CTRL_OFFSET 12 355#define AVBUF_EXTERNAL_DIVIDER 2 356#define AVBUF_VIDEO_REF_CTRL 0x00000070 357#define AVBUF_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007 358#define AVBUF_VPLL_SRC_SEL 0 359#define AVBUF_DPLL_SRC_SEL 2 360#define AVBUF_RPLL_TO_FPD_SRC_SEL 3 361#define AVBUF_INPUT_REF_CLK 3333333333 362#define AVBUF_PLL_OUT_FREQ 1450000000 363#define AVBUF_INPUT_FREQ_PRECISION 100 364#define AVBUF_PRECISION 16 365#define AVBUF_SHIFT_DECIMAL BIT(16) 366#define AVBUF_DECIMAL (AVBUF_SHIFT_DECIMAL - 1) 367#define AVBUF_ENABLE_BIT 1 368#define AVBUF_DISABLE_BIT 0 369#define AVBUF_PLL_CTRL_BYPASS_SHIFT 3 370#define AVBUF_PLL_CTRL_FBDIV_SHIFT 8 371#define AVBUF_PLL_CTRL_DIV2_SHIFT 16 372#define AVBUF_PLL_CTRL_PRE_SRC_SHIFT 20 373#define AVBUF_PLL_CTRL 0x00000020 374#define AVBUF_PLL_CFG_CP_SHIFT 5 375#define AVBUF_PLL_CFG_RES_SHIFT 0 376#define AVBUF_PLL_CFG_LFHF_SHIFT 10 377#define AVBUF_PLL_CFG_LOCK_DLY_SHIFT 25 378#define AVBUF_PLL_CFG_LOCK_CNT_SHIFT 13 379#define AVBUF_PLL_FRAC_CFG 0x00000028 380#define AVBUF_PLL_FRAC_CFG_ENABLED_SHIFT 31 381#define AVBUF_PLL_FRAC_CFG_DATA_SHIFT 0 382#define AVBUF_PLL_CTRL_RESET_MASK 0x00000001 383#define AVBUF_PLL_CTRL_RESET_SHIFT 0 384#define AVBUF_PLL_STATUS 0x00000044 385#define AVBUF_REG_OFFSET 4 386#define AVBUF_PLL_CTRL_BYPASS_MASK 0x00000008 387#define AVBUF_PLL_CTRL_BYPASS_SHIFT 3 388#define AVBUF_DOMAIN_SWITCH_CTRL 0x00000044 389#define AVBUF_DOMAIN_SWITCH_DIVISOR0_MASK 0x00003F00 390#define AVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT 8 391#define AVBUF_PLL_CFG 0x00000024 392#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0 393#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000 394#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24 395#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000 396#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 397#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00 398#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 399#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000 400#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24 401 402#define DP_INTERRUPT_SIG_STATE 0x0130 403#define DP_INTR_STATUS 0x03A0 404#define DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001 405#define DP_INTR_HPD_EVENT_MASK 0x00000002 406#define DP_INTR_HPD_PULSE_DETECTED_MASK 0x00000010 407#define DP_HPD_DURATION 0x0150 408#define DP_FORCE_SCRAMBLER_RESET 0x00C0 409#define DP_ENABLE_MAIN_STREAM 0x0084 410#define DP_IS_CONNECTED_MAX_TIMEOUT_COUNT 50 411#define DP_0_LINK_RATE 20 412#define DP_0_LANE_COUNT 1 413#define DP_ENHANCED_FRAME_EN 0x0008 414#define DP_LANE_COUNT_SET 0x0004 415#define DP_LINK_BW_SET_162GBPS 0x06 416#define DP_LINK_BW_SET_270GBPS 0x0A 417#define DP_LINK_BW_SET_540GBPS 0x14 418#define DP_LINK_BW_SET 0x0000 419#define DP_DOWNSPREAD_CTRL 0x0018 420#define DP_SCRAMBLING_DISABLE 0x0014 421#define DP_AUX_CMD_READ 0x9 422#define DP_AUX_CMD_WRITE 0x8 423#define DP_AUX_CMD_I2C_READ 0x1 424#define DP_AUX_CMD_I2C_READ_MOT 0x5 425#define DP_AUX_CMD_I2C_WRITE 0x0 426#define DP_AUX_CMD_I2C_WRITE_MOT 0x4 427#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 428#define DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004 429#define DP_REPLY_STATUS 0x014C 430#define DP_AUX_MAX_TIMEOUT_COUNT 50 431#define DP_AUX_MAX_DEFER_COUNT 50 432#define DP_AUX_ADDRESS 0x0108 433#define DP_AUX_WRITE_FIFO 0x0104 434#define DP_AUX_CMD 0x0100 435#define DP_AUX_CMD_SHIFT 8 436#define DP_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F 437#define DP_AUX_REPLY_CODE 0x0138 438#define DP_AUX_REPLY_CODE_DEFER 0x2 439#define DP_AUX_REPLY_CODE_I2C_DEFER 0x8 440#define DP_AUX_REPLY_CODE_NACK 0x1 441#define DP_AUX_REPLY_CODE_I2C_NACK 0x4 442#define DP_REPLY_DATA_COUNT 0x0148 443#define DP_AUX_REPLY_DATA 0x0134 444#define DP_LANE_COUNT_SET_1 0x01 445#define DP_LANE_COUNT_SET_2 0x02 446#define DP_MAXIMUM_PE_LEVEL 2 447#define DP_MAXIMUM_VS_LEVEL 3 448#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB 0x0 449#define DP_MAIN_STREAM_MISC0_BDC_6BPC 0x0 450#define DP_MAIN_STREAM_MISC0_BDC_8BPC 0x1 451#define DP_MAIN_STREAM_MISC0_BDC_10BPC 0x2 452#define DP_MAIN_STREAM_MISC0_BDC_12BPC 0x3 453#define DP_MAIN_STREAM_MISC0_BDC_16BPC 0x4 454#define DP_MAIN_STREAM_MISC0_BDC_SHIFT 5 455#define DP_PHY_CONFIG_TX_PHY_8B10BEN_MASK 0x0010000 456#define DP_PHY_CONFIG_PHY_RESET_MASK 0x0000001 457#define DP_ENABLE_MAIN_STREAM 0x0084 458#define DP_SOFT_RESET 0x001C 459#define DP_MAIN_STREAM_HTOTAL 0x0180 460#define DP_MAIN_STREAM_VTOTAL 0x0184 461#define DP_MAIN_STREAM_POLARITY 0x0188 462#define DP_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT 1 463#define DP_MAIN_STREAM_HSWIDTH 0x018C 464#define DP_MAIN_STREAM_VSWIDTH 0x0190 465#define DP_MAIN_STREAM_HRES 0x0194 466#define DP_MAIN_STREAM_VRES 0x0198 467#define DP_MAIN_STREAM_HSTART 0x019C 468#define DP_MAIN_STREAM_VSTART 0x01A0 469#define DP_MAIN_STREAM_MISC0 0x01A4 470#define DP_MAIN_STREAM_MISC1 0x01A8 471#define DP_M_VID 0x01AC 472#define DP_N_VID 0x01B4 473#define DP_USER_PIXEL_WIDTH 0x01B8 474#define DP_USER_DATA_COUNT_PER_LANE 0x01BC 475#define DP_TU_SIZE 0x01B0 476#define DP_MIN_BYTES_PER_TU 0x01C4 477#define DP_FRAC_BYTES_PER_TU 0x01C8 478#define DP_INIT_WAIT 0x01CC 479#define DP_PHY_CLOCK_SELECT_162GBPS 0x1 480#define DP_PHY_CLOCK_SELECT_270GBPS 0x3 481#define DP_PHY_CLOCK_SELECT_540GBPS 0x5 482#define DP_PHY_STATUS 0x0280 483#define DP_PHY_STATUS_ALL_LANES_READY_MASK 0x00000013 484#define DP_PHY_STATUS_GT_PLL_LOCK_MASK 0x00000010 485#define DP_PHY_STATUS_RESET_LANE_0_DONE_MASK 0x00000001 486#define DP_INTR_HPD_IRQ_MASK 0x00000001 487#define DP_INTR_MASK 0x03A4 488#define DP_DP_ENABLE 0x1 489#define DP_PHY_CONFIG_GT_ALL_RESET_MASK 0x0000003 490#define DP_PHY_CLOCK_SELECT 0x0234 491#define DP_AUX_CLK_DIVIDER_VAL_MASK 0x000000FF 492#define DP_AUX_CLK_DIVIDER 0x010C 493#define DP_DISABLE 0x0 494#define DP_ENABLE 0x0080 495#define DP_SOFT_RESET_EN 0x1 496#define DP_PHY_CONFIG 0x0200 497#define DP_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001 498#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 499#define DP_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008 500#define DP_AUX_MAX_WAIT 20000 501 502#define DP_DPCD_SINK_COUNT 0x00200 503#define DP_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 504#define DP_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 505#define DP_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 506#define DP_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 507#define DP_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 508#define DP_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 509#define DP_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 510#define DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK 0x01 511#define DP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 512#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 513#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 514#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C 515#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 516#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 517#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 518#define DP_DPCD_TRAINING_LANE0_SET 0x00103 519#define DP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 520#define DP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 521#define DP_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 522#define DP_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 523#define DP_DPCD_RECEIVER_CAP_FIELD_START 0x00000 524#define DP_DPCD_MAX_LINK_RATE 0x00001 525#define DP_DPCD_MAX_LANE_COUNT 0x00002 526#define DP_DPCD_MAX_LANE_COUNT_MASK 0x1F 527#define DP_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 528#define DP_DPCD_MAX_DOWNSPREAD 0x00003 529#define DP_DPCD_MAX_DOWNSPREAD_MASK 0x01 530#define DP_DPCD_LANE_COUNT_SET 0x00101 531#define DP_DPCD_ENHANCED_FRAME_EN_MASK 0x80 532#define DP_DPCD_LINK_BW_SET 0x00100 533#define DP_DPCD_DOWNSPREAD_CTRL 0x00107 534#define DP_DPCD_SPREAD_AMP_MASK 0x10 535#define DP_DPCD_LANE_COUNT_SET_MASK 0x1F 536#define DP_DPCD_TPS3_SUPPORT_MASK 0x40 537#define DP_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E 538#define DP_DPCD_SINK_COUNT_HIGH_MASK 0x80 539#define DP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1 540#define DP_DPCD_SINK_COUNT_LOW_MASK 0x3F 541#define DP_DPCD_TP_SET 0x00102 542 543#define SERDES_BASEADDR 0xFD400000 544#define SERDES_L0_TX_MARGININGF 0x0CC0 545#define SERDES_L0_TX_DEEMPHASIS 0x0048 546#define SERDES_LANE_OFFSET 0x4000 547 548#define DPDMA_TRIGGER_EN 1U 549#define DPDMA_RETRIGGER_EN 2U 550#define DPDMA_DESC_PREAMBLE 0xA5U 551#define DPDMA_DESC_IGNR_DONE 0x400U 552#define DPDMA_DESC_LAST_FRAME 0x200000U 553#define DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT 18 554#define DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH 32U 555#define DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT 16U 556#define DPDMA_CH0_DSCR_STRT_ADDR 0X0204U 557#define DPDMA_CH_OFFSET 0x100U 558#define DPDMA_CH0_CNTL 0x0218U 559#define DPDMA_CH3_CNTL 0x0518U 560#define DPDMA_CH0_DSCR_STRT_ADDRE 0x0200U 561#define DPDMA_CH3_DSCR_STRT_ADDR 0x0504 562#define DPDMA_CH3_DSCR_STRT_ADDRE 0x0500 563#define DPDMA_CH_CNTL_EN_MASK 0x1U 564#define DPDMA_CH_CNTL_PAUSE_MASK 0x2U 565#define DPDMA_GBL 0x0104U 566#define DPDMA_GBL_TRG_CH3_MASK 0x8 567#define DPDMA_TRIGGER_DONE 0U 568#define DPDMA_CH_CNTL_EN_MASK 0x1U 569#define DPDMA_CH_CNTL_PAUSE_MASK 0x2U 570#define DPDMA_CH_CNTL_QOS_DATA_RD_SHIFT 10U 571#define DPDMA_CH_CNTL_QOS_DATA_RD_MASK 0x3C00U 572#define DPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT 6U 573#define DPDMA_CH_CNTL_QOS_DSCR_RD_MASK 0x03C0U 574#define DPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT 2U 575#define DPDMA_CH_CNTL_QOS_DSCR_WR_MASK 0x3CU 576#define DPDMA_CH_OFFSET 0x100U 577#define DPDMA_WAIT_TIMEOUT 10000U 578#define DPDMA_AUDIO_ALIGNMENT 128U 579#define DPDMA_VIDEO_CHANNEL0 0U 580#define DPDMA_VIDEO_CHANNEL1 1U 581#define DPDMA_VIDEO_CHANNEL2 2U 582#define DPDMA_GRAPHICS_CHANNEL 3U 583#define DPDMA_AUDIO_CHANNEL0 4U 584#define DPDMA_AUDIO_CHANNEL1 5U 585#define DPDMA_DESC_PREAMBLE 0xA5U 586#define DPDMA_DESC_IGNR_DONE 0x400U 587#define DPDMA_DESC_UPDATE 0x200U 588#define DPDMA_DESC_COMP_INTR 0x100U 589#define DPDMA_DESC_LAST_FRAME 0x200000U 590#define DPDMA_DESC_DONE_SHIFT 31U 591#define DPDMA_QOS_MIN 4U 592#define DPDMA_QOS_MAX 11U 593#define DPDMA_BASE_ADDRESS 0xFD4C0000 594#define DPDMA_ISR 0x0004U 595#define DPDMA_IEN 0x000CU 596#define DPDMA_ISR_VSYNC_INT_MASK 0x08000000 597 598#define CLK_FPD_BASEADDR 0xFD1A0000 599#define VIDEO_REF_CTRL 0x00000070 600#define VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007 601#define PLL_OUT_FREQ 1450000000 602#define INPUT_FREQ_PRECISION 100 603#define PRECISION 16 604#define SHIFT_DECIMAL BIT(16) 605#define ENABLE_BIT 1 606#define DISABLE_BIT 0 607#define PLL_CTRL_BYPASS_SHIFT 3 608#define PLL_CTRL_FBDIV_SHIFT 8 609#define PLL_CTRL_DIV2_SHIFT 16 610#define PLL_CTRL_PRE_SRC_SHIFT 20 611#define PLL_CTRL 0x00000020 612#define VPLL_CTRL 0x00000038 613#define PLL_CFG 0x00000024 614#define VPLL 2 615#define VPLL_CFG 0x0000003C 616#define VPLL_CFG_CP 4 617#define VPLL_CFG_RES 6 618#define VPLL_CFG_LFHF 3 619#define VPLL_CFG_LOCK_DLY 63 620#define VPLL_CFG_LOCK_CNT 600 621#define PLL_STATUS_VPLL_LOCK 2 622#define PLL_CFG_CP_SHIFT 5 623#define PLL_CFG_RES_SHIFT 0 624#define PLL_CFG_LFHF_SHIFT 10 625#define PLL_CFG_LOCK_DLY_SHIFT 25 626#define PLL_CFG_LOCK_CNT_SHIFT 13 627#define PLL_FRAC_CFG 0x00000028 628#define VPLL_FRAC_CFG 0x00000040 629#define PLL_FRAC_CFG_ENABLED_SHIFT 31 630#define PLL_FRAC_CFG_DATA_SHIFT 0 631#define PLL_CTRL_RESET_MASK 0x00000001 632#define PLL_CTRL_RESET_SHIFT 0 633#define PLL_STATUS 0x00000044 634#define REG_OFFSET 4 635#define PLL_CTRL_BYPASS_MASK 0x00000008 636#define PLL_CTRL_BYPASS_SHIFT 3 637#define DOMAIN_SWITCH_CTRL 0x00000044 638#define DOMAIN_SWITCH_DIVISOR0_MASK 0x00003F00 639#define DOMAIN_SWITCH_DIVISOR0_SHIFT 8 640#define VIDEO_REF_CTRL_CLKACT_MASK 0x01000000 641#define VIDEO_REF_CTRL_CLKACT_SHIFT 24 642#define VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000 643#define VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 644#define VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00 645#define VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 646#define PSS_REF_CLK 0 647#define FPD_CTRL_OFFSET 12 648#define VIDC_VM_NUM_SUPPORTED 2 649 650static const u32 vs[4][4] = { 651 { 0x2a, 0x27, 0x24, 0x20 }, 652 { 0x27, 0x23, 0x20, 0xff }, 653 { 0x24, 0x20, 0xff, 0xff }, 654 { 0xff, 0xff, 0xff, 0xff }, 655}; 656 657static const u32 pe[4][4] = { 658 { 0x02, 0x02, 0x02, 0x02 }, 659 { 0x01, 0x01, 0x01, 0xff }, 660 { 0x00, 0x00, 0xff, 0xff }, 661 { 0xff, 0xff, 0xff, 0xff }, 662}; 663 664const struct video_timing_mode vidc_video_timing_modes[VIDC_VM_NUM_SUPPORTED] = { 665 { VIDC_VM_640x480_60_P, "640x480@60Hz", VIDC_FR_60HZ, 666 {640, 16, 96, 48, 800, 0, 667 480, 10, 2, 33, 525, 0, 0, 0, 0, 0} }, 668 { VIDC_VM_1024x768_60_P, "1024x768@60Hz", VIDC_FR_60HZ, 669 {1024, 24, 136, 160, 1344, 0, 670 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} }, 671}; 672 673const struct av_buf_vid_attribute avbuf_supported_formats[] = { 674 /* Non-Live Graphics formats */ 675 { RGBA8888, 0, INTERLEAVED, 676 {AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF}, 677 0, 1, 0, 32}, 678}; 679 680#endif 681