Searched refs:od (Results 1 - 24 of 24) sorted by relevance

/u-boot/test/dm/
H A Dk210_pll.c16 u64 f, r, od, max_r, inv_ratio; local
27 for (od = 1; od <= 16; od++) {
34 r * od);
40 best->od = od;
55 return (u32)ours->f * theirs->r * theirs->od !=
56 (u32)theirs->f * ours->r * ours->od;
/u-boot/board/freescale/common/
H A Dics307_clk.c54 unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; local
59 od = ics307_s_to_od[odp];
60 if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
64 vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
70 tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
107 unsigned long od = ics307_s_to_od[cw0 & 0x7]; local
126 freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
/u-boot/include/k210/
H A Dpll.h13 u8 od; member in struct:k210_pll_config
/u-boot/arch/arm/cpu/armv8/
H A Dsha1_ce_core.S96 add_update c, od, k0, 9, 10, 11, 8
98 add_update c, od, k0, 11, 8, 9, 10
101 add_update p, od, k1, 9, 10, 11, 8
103 add_update p, od, k1, 11, 8, 9, 10
105 add_update p, od, k2, 9, 10, 11, 8
108 add_update m, od, k2, 11, 8, 9, 10
110 add_update m, od, k2, 9, 10, 11, 8
113 add_update p, od, k3, 11, 8, 9, 10
115 add_only p, od, k3, 10
117 add_only p, od
[all...]
/u-boot/drivers/pinctrl/
H A Dpinctrl-sti.c33 /* oe = 0, pu = 0, od = 0 */
35 /* oe = 0, pu = 1, od = 0 */
37 /* oe = 1, pu = 0, od = 0 */
39 /* oe = 1, pu = 1, od = 0 */
41 /* oe = 1, pu = 0, od = 1 */
43 /* oe = 1, pu = 1, od = 1 */
98 int oe = 0, pu = 0, od = 0; local
132 oe = 0; pu = 0; od = 0;
135 oe = 0; pu = 1; od = 0;
138 oe = 1; pu = 0; od
[all...]
/u-boot/drivers/video/meson/
H A Dmeson_vclk.c411 static inline unsigned int pll_od_to_reg(unsigned int od) argument
413 switch (od) {
632 unsigned int *od)
635 for (*od = 16 ; *od > 1 ; *od >>= 1) {
636 *m = meson_hdmi_pll_get_m(priv, freq * *od);
639 *frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
641 debug("PLL params for %dkHz: m=%x frac=%x od=%d\n",
642 freq, *m, *frac, *od);
628 meson_hdmi_pll_find_params(struct meson_vpu_priv *priv, unsigned int freq, unsigned int *m, unsigned int *frac, unsigned int *od) argument
655 unsigned int od, m, frac; local
670 unsigned int od, m, frac, od1, od2, od3; local
[all...]
/u-boot/drivers/clk/
H A Dclk_k210.c478 * |/od|
486 * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
489 * rate = (rate_in * f) / (r * od).
491 * rate / rate_in = f / (r * od)
493 * abs_error = abs((rate / rate_in) - (f / (r * od))).
495 * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
497 * error = abs(1 - f / (r * od)) / (rate / rate_in)
498 * error = abs(1 - (f * rate_in) / (r * od * rate))
500 * error = abs((f * inv_ratio) / (r * od) - 1)
503 * r and od ar
669 u64 r, f, od; local
916 u64 r, f, od; local
[all...]
/u-boot/drivers/pinctrl/tegra/
H A Dpinmux-common.c41 #define pmux_pin_od_isvalid(od) \
42 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
282 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) argument
287 if (od == PMUX_PIN_OD_DEFAULT)
290 /* Error check on pin and od */
292 assert(pmux_pin_od_isvalid(od));
295 if (od == PMUX_PIN_OD_ENABLE)
444 pinmux_set_od(pin, config->od);
H A Dpinctrl-tegra.c102 pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0);
/u-boot/drivers/clk/meson/
H A Daxg.c208 u16 n, m, od; local
233 od = PARM_GET(pod->width, pod->shift, reg);
235 return ((parent_rate_mhz * m / n) >> od) * 1000000;
H A Dg12a.c693 u16 n, m, od, frac; local
725 od = PARM_GET(pod->width, pod->shift, reg);
744 return (DIV_ROUND_UP_ULL(rate, n) >> od) * 1000000;
758 u16 n, m, od; local
772 od = PARM_GET(pod->width, pod->shift, reg);
774 return ((parent_rate_mhz * m / n) / 2 / od / 2) * 1000000;
H A Dgxbb.c696 u16 n, m, od; local
721 od = PARM_GET(pod->width, pod->shift, reg);
723 return ((parent_rate_mhz * m / n) >> od) * 1000000;
/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpinmux.h122 u32 od:2; /* open-drain or push-pull driver */ member in struct:pmux_pingrp_config
/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c362 #define M_N_OD(m, n, od) \
363 ((((m) - 1) << 19) | (((n) - 1) << 13) | (((od) - 1) << 9))
371 static void pll_init_one(int pll, int m, int n, int od) argument
376 setbits_le32(pll_reg, M_N_OD(m, n, od) | XPLLEN);
/u-boot/board/nvidia/dalmore/
H A Dpinmux-config-dalmore.h17 .od = PMUX_PIN_OD_DEFAULT, \
29 .od = PMUX_PIN_OD_##_od, \
53 .od = PMUX_PIN_OD_DEFAULT, \
65 .od = PMUX_PIN_OD_##_od, \
/u-boot/board/avionic-design/common/
H A Dpinmux-config-tamonten-ng.h18 .od = PMUX_PIN_OD_DEFAULT, \
30 .od = PMUX_PIN_OD_##_od, \
42 .od = PMUX_PIN_OD_DEFAULT, \
/u-boot/board/nvidia/cardhu/
H A Dpinmux-config-cardhu.h17 .od = PMUX_PIN_OD_DEFAULT, \
29 .od = PMUX_PIN_OD_##_od, \
41 .od = PMUX_PIN_OD_DEFAULT, \
/u-boot/board/toradex/colibri_t30/
H A Dpinmux-config-colibri_t30.h19 .od = PMUX_PIN_OD_DEFAULT, \
31 .od = PMUX_PIN_OD_##_od, \
43 .od = PMUX_PIN_OD_DEFAULT, \
/u-boot/board/toradex/apalis_t30/
H A Dpinmux-config-apalis_t30.h19 .od = PMUX_PIN_OD_DEFAULT, \
31 .od = PMUX_PIN_OD_##_od, \
43 .od = PMUX_PIN_OD_DEFAULT, \
/u-boot/board/cei/cei-tk1-som/
H A Dpinmux-config-cei-tk1-som.h75 .od = PMUX_PIN_OD_##_od, \
82 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
/u-boot/board/nvidia/jetson-tk1/
H A Dpinmux-config-jetson-tk1.h83 .od = PMUX_PIN_OD_##_od, \
90 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
/u-boot/board/nvidia/nyan-big/
H A Dpinmux-config-nyan-big.h79 .od = PMUX_PIN_OD_##_od, \
86 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
/u-boot/board/nvidia/venice2/
H A Dpinmux-config-venice2.h90 .od = PMUX_PIN_OD_##_od, \
97 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
/u-boot/board/toradex/apalis-tk1/
H A Dpinmux-config-apalis-tk1.h63 .od = PMUX_PIN_OD_##_od, \
70 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */

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