drivers/clk/clk_k210.c

478  *        |/od|
486  * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
489  *   rate = (rate_in * f) / (r * od).
491  *   rate / rate_in = f / (r * od)
493  *   abs_error = abs((rate / rate_in) - (f / (r * od))).
495  *   error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
497  *   error = abs(1 - f / (r * od)) / (rate / rate_in)
498  *   error = abs(1 - (f * rate_in) / (r * od * rate))
500  *   error = abs((f * inv_ratio) / (r * od) - 1)
503  * r and od are four bits each, while f is six bits. Because r and od are
516  * The r and od factors are stored in a table. This is to make it easy to find
555 #define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
669 	u64 r, f, od;
673 	 * VCO frequency. These are not the same limits as below because od can
704 	od = 0;
710 		 * Whether we swapped r and od while enforcing frequency limits
717 		u64 last_od = od;
721 		 * Try the next largest value for f (or r and od) and
732 				od = UNPACK_OD(factors[i]);
734 				 r * od == last_r * last_od);
737 			f = (r * od * ratio + BIT(31)) >> 32;
746 			/* Get the next r/od pair in factors */
747 			while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
750 				od = UNPACK_OD(factors[i]);
758 			 * there is no r * od = X+1. For the converse, when X.Y
761 			err = abs(r * od - goal);
766 				od = last_od;
772 		 * aren't in spec, try swapping r and od. If everything is
783 			 * effect of od.
797 				r = od;
798 				od = tmp;
811 				if (r * od == new_r * new_od) {
813 					od = new_od;
833 				if (r * od != new_r * new_od) {
836 						od = new_od;
848 		error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
855 			best->od = od;
879 	log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
883 				       config.r * config.od);
896 	    |  FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
916 	u64 r, f, od;
927 	od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
929 	return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);