1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 - BayLibre, SAS
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 */
7
8#include <log.h>
9#include <asm/arch/clock-axg.h>
10#include <asm/io.h>
11#include <clk-uclass.h>
12#include <dm.h>
13#include <regmap.h>
14#include <syscon.h>
15#include <div64.h>
16#include <dt-bindings/clock/axg-clkc.h>
17#include <linux/bitops.h>
18#include "clk_meson.h"
19#include <linux/err.h>
20
21#define XTAL_RATE 24000000
22
23struct meson_clk {
24	struct regmap *map;
25};
26
27static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
28
29static struct meson_gate gates[] = {
30	/* Everything Else (EE) domain gates */
31	MESON_GATE(CLKID_SPICC0, HHI_GCLK_MPEG0, 8),
32	MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
33	MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
34	MESON_GATE(CLKID_SPICC1, HHI_GCLK_MPEG0, 15),
35	MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
36	MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
37	MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
38	MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
39
40	/* Always On (AO) domain gates */
41	MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
42
43	/* PLL Gates */
44	/* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
45	MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
46	/* CLKID_CLK81 is critical for the system */
47
48	/* Peripheral Gates */
49	MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
50	MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
51};
52
53static int meson_set_gate(struct clk *clk, bool on)
54{
55	struct meson_clk *priv = dev_get_priv(clk->dev);
56	struct meson_gate *gate;
57
58	if (clk->id >= ARRAY_SIZE(gates))
59		return -ENOENT;
60
61	gate = &gates[clk->id];
62
63	if (gate->reg == 0)
64		return 0;
65
66	regmap_update_bits(priv->map, gate->reg,
67			   BIT(gate->bit), on ? BIT(gate->bit) : 0);
68
69	return 0;
70}
71
72static int meson_clk_enable(struct clk *clk)
73{
74	return meson_set_gate(clk, true);
75}
76
77static int meson_clk_disable(struct clk *clk)
78{
79	return meson_set_gate(clk, false);
80}
81
82static unsigned long meson_clk81_get_rate(struct clk *clk)
83{
84	struct meson_clk *priv = dev_get_priv(clk->dev);
85	unsigned long parent_rate;
86	uint reg;
87	int parents[] = {
88		-1,
89		-1,
90		CLKID_FCLK_DIV7,
91		CLKID_MPLL1,
92		CLKID_MPLL2,
93		CLKID_FCLK_DIV4,
94		CLKID_FCLK_DIV3,
95		CLKID_FCLK_DIV5
96	};
97
98	/* mux */
99	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
100	reg = (reg >> 12) & 7;
101
102	switch (reg) {
103	case 0:
104		parent_rate = XTAL_RATE;
105		break;
106	case 1:
107		return -ENOENT;
108	default:
109		parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
110	}
111
112	/* divider */
113	regmap_read(priv->map, HHI_MPEG_CLK_CNTL, &reg);
114	reg = reg & ((1 << 7) - 1);
115
116	return parent_rate / reg;
117}
118
119static long mpll_rate_from_params(unsigned long parent_rate,
120				  unsigned long sdm,
121				  unsigned long n2)
122{
123	unsigned long divisor = (SDM_DEN * n2) + sdm;
124
125	if (n2 < N2_MIN)
126		return -EINVAL;
127
128	return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
129}
130
131static struct parm meson_mpll0_parm[3] = {
132	{HHI_MPLL_CNTL7, 0, 14}, /* psdm */
133	{HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
134};
135
136static struct parm meson_mpll1_parm[3] = {
137	{HHI_MPLL_CNTL8, 0, 14}, /* psdm */
138	{HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
139};
140
141static struct parm meson_mpll2_parm[3] = {
142	{HHI_MPLL_CNTL9, 0, 14}, /* psdm */
143	{HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
144};
145
146/*
147 * MultiPhase Locked Loops are outputs from a PLL with additional frequency
148 * scaling capabilities. MPLL rates are calculated as:
149 *
150 * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
151 */
152static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
153{
154	struct meson_clk *priv = dev_get_priv(clk->dev);
155	struct parm *psdm, *pn2;
156	unsigned long sdm, n2;
157	unsigned long parent_rate;
158	uint reg;
159
160	switch (id) {
161	case CLKID_MPLL0:
162		psdm = &meson_mpll0_parm[0];
163		pn2 = &meson_mpll0_parm[1];
164		break;
165	case CLKID_MPLL1:
166		psdm = &meson_mpll1_parm[0];
167		pn2 = &meson_mpll1_parm[1];
168		break;
169	case CLKID_MPLL2:
170		psdm = &meson_mpll2_parm[0];
171		pn2 = &meson_mpll2_parm[1];
172		break;
173	default:
174		return -ENOENT;
175	}
176
177	parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
178	if (IS_ERR_VALUE(parent_rate))
179		return parent_rate;
180
181	regmap_read(priv->map, psdm->reg_off, &reg);
182	sdm = PARM_GET(psdm->width, psdm->shift, reg);
183
184	regmap_read(priv->map, pn2->reg_off, &reg);
185	n2 = PARM_GET(pn2->width, pn2->shift, reg);
186
187	return mpll_rate_from_params(parent_rate, sdm, n2);
188}
189
190static struct parm meson_fixed_pll_parm[3] = {
191	{HHI_MPLL_CNTL, 0, 9}, /* pm */
192	{HHI_MPLL_CNTL, 9, 5}, /* pn */
193	{HHI_MPLL_CNTL, 16, 2}, /* pod */
194};
195
196static struct parm meson_sys_pll_parm[3] = {
197	{HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
198	{HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
199	{HHI_SYS_PLL_CNTL, 16, 2}, /* pod */
200};
201
202static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
203{
204	struct meson_clk *priv = dev_get_priv(clk->dev);
205	struct parm *pm, *pn, *pod;
206	unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
207	u16 n, m, od;
208	uint reg;
209
210	switch (id) {
211	case CLKID_FIXED_PLL:
212		pm = &meson_fixed_pll_parm[0];
213		pn = &meson_fixed_pll_parm[1];
214		pod = &meson_fixed_pll_parm[2];
215		break;
216	case CLKID_SYS_PLL:
217		pm = &meson_sys_pll_parm[0];
218		pn = &meson_sys_pll_parm[1];
219		pod = &meson_sys_pll_parm[2];
220		break;
221	default:
222		return -ENOENT;
223	}
224
225	regmap_read(priv->map, pn->reg_off, &reg);
226	n = PARM_GET(pn->width, pn->shift, reg);
227
228	regmap_read(priv->map, pm->reg_off, &reg);
229	m = PARM_GET(pm->width, pm->shift, reg);
230
231	regmap_read(priv->map, pod->reg_off, &reg);
232	od = PARM_GET(pod->width, pod->shift, reg);
233
234	return ((parent_rate_mhz * m / n) >> od) * 1000000;
235}
236
237static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
238{
239	ulong rate;
240
241	switch (id) {
242	case CLKID_FIXED_PLL:
243	case CLKID_SYS_PLL:
244		rate = meson_pll_get_rate(clk, id);
245		break;
246	case CLKID_FCLK_DIV2:
247		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
248		break;
249	case CLKID_FCLK_DIV3:
250		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
251		break;
252	case CLKID_FCLK_DIV4:
253		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
254		break;
255	case CLKID_FCLK_DIV5:
256		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
257		break;
258	case CLKID_FCLK_DIV7:
259		rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
260		break;
261	case CLKID_MPLL0:
262	case CLKID_MPLL1:
263	case CLKID_MPLL2:
264		rate = meson_mpll_get_rate(clk, id);
265		break;
266	case CLKID_CLK81:
267		rate = meson_clk81_get_rate(clk);
268		break;
269	default:
270		if (gates[id].reg != 0) {
271			/* a clock gate */
272			rate = meson_clk81_get_rate(clk);
273			break;
274		}
275		return -ENOENT;
276	}
277
278	debug("clock %lu has rate %lu\n", id, rate);
279	return rate;
280}
281
282static ulong meson_clk_get_rate(struct clk *clk)
283{
284	return meson_clk_get_rate_by_id(clk, clk->id);
285}
286
287static int meson_clk_probe(struct udevice *dev)
288{
289	struct meson_clk *priv = dev_get_priv(dev);
290
291	priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
292	if (IS_ERR(priv->map))
293		return PTR_ERR(priv->map);
294
295	/*
296	 * Depending on the boot src, the state of the MMC clock might
297	 * be different. Reset it to make sure we won't get stuck
298	 */
299	regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
300	regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
301
302	debug("meson-clk-axg: probed\n");
303
304	return 0;
305}
306
307static struct clk_ops meson_clk_ops = {
308	.disable	= meson_clk_disable,
309	.enable		= meson_clk_enable,
310	.get_rate	= meson_clk_get_rate,
311};
312
313static const struct udevice_id meson_clk_ids[] = {
314	{ .compatible = "amlogic,axg-clkc" },
315	{ }
316};
317
318U_BOOT_DRIVER(meson_clk_axg) = {
319	.name		= "meson_clk_axg",
320	.id		= UCLASS_CLK,
321	.of_match	= meson_clk_ids,
322	.priv_auto	= sizeof(struct meson_clk),
323	.ops		= &meson_clk_ops,
324	.probe		= meson_clk_probe,
325};
326