Searched refs:mr (Results 1 - 25 of 85) sorted by relevance

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/u-boot/arch/arm/mach-at91/
H A Dsdram.c37 writel(AT91_SDRAMC_MODE_NOP, &reg->mr);
41 writel(AT91_SDRAMC_MODE_PRECHARGE, &reg->mr);
49 writel(AT91_SDRAMC_MODE_REFRESH, &reg->mr);
57 writel(AT91_SDRAMC_MODE_LMR, &reg->mr);
65 writel(AT91_SDRAMC_MODE_NORMAL, &reg->mr);
H A Dphy.c29 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
38 AT91_RSTC_MR_URSTEN, &rstc->mr);
56 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pit.h16 u32 mr; /* 0x00 Mode Register */ member in struct:at91_pit
H A Dat91_dbu.h17 u32 mr; /* Mode Register RW */ member in struct:at91_dbu
H A Dat91_rstc.h24 u32 mr; /* Reset Controller Mode Register */ member in struct:at91_rstc
H A Dat91_wdt.h24 u32 mr; member in struct:at91_wdt
H A Dat91_mc.h31 u32 mr; /* 0x00 SDRAMC Mode Register */ member in struct:at91_sdramc
63 u32 mr; /* 0x00 SDRAMC Mode Register */ member in struct:at91_bfc
/u-boot/post/lib_powerpc/
H A Dasm.S26 mr r3, r4
27 mr r4, r5
49 mr r3, r4
50 mr r4, r5
51 mr r5, r6
72 mr r3, r5
73 mr r4, r6
93 mr r3, r5
119 mr r3, r6
149 mr r
[all...]
/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c48 writel(0x263, &mctl_ctl->mr[0]);
49 writel(0x4, &mctl_ctl->mr[1]);
50 writel(0x0, &mctl_ctl->mr[2]);
51 writel(0x0, &mctl_ctl->mr[3]);
H A Dlpddr3_stock.c48 writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */
49 writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */
50 writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */
H A Dddr3_1333.c48 writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
49 writel(0x40, &mctl_ctl->mr[1]);
50 writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
51 writel(0x0, &mctl_ctl->mr[3]);
/u-boot/arch/arm/mach-at91/armv7/
H A Dtimer.c51 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
H A Dcpu.c47 writel(cpiv + 0x1000, &pit->mr);
/u-boot/arch/arm/mach-imx/imx8/
H A Dcpu.c477 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, argument
484 owned = sc_rm_is_memreg_owned(-1, mr);
486 ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
514 sc_rm_mr_t mr; local
525 for (mr = 0; mr < 64; mr++) {
526 err = get_owned_memreg(mr, &start, &end);
552 sc_rm_mr_t mr; local
563 for (mr
619 sc_rm_mr_t mr; local
726 sc_rm_mr_t mr; local
[all...]
/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c42 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
114 writel(timings->mr, &sdrc_base->cs[cs].mr);
189 timings.mr = readl(&sdrc_base->cs[CS0].mr);
/u-boot/arch/powerpc/lib/
H A Dticks.S37 mr r14, r3 /* save tick count */
/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c363 u16 mr[4] = { 0, }; local
461 mr[0] = DDR3_MR0_PPD_FAST_EXIT | DDR3_MR0_WR(tWR) |
463 mr[1] = DDR3_MR1_RTT120OHM;
464 mr[2] = DDR3_MR2_TWL(CWL);
465 mr[3] = 0;
484 writel(MCTL_INIT3_MR(mr[0]) | MCTL_INIT3_EMR(mr[1]),
486 writel(MCTL_INIT4_EMR2(mr[2]) | MCTL_INIT4_EMR3(mr[3]),
505 writel(MCTL_INIT3_MR(mr[
[all...]
/u-boot/drivers/dma/
H A Dfsl_dma.c73 out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
112 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
116 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dcpu.c39 writel(cpiv + 0x1000, &pit->mr);
H A Dtimer.c47 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
/u-boot/arch/arm/mach-omap2/am33xx/
H A Dddr.c43 u32 mr; local
48 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
49 debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
50 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
51 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
52 ((mr & 0xff000000) >> 24) == (mr
[all...]
/u-boot/arch/arm/mach-omap2/
H A Demif-common.c62 u32 mr; local
68 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
70 mr = readl(&emif->emif_lpddr2_mode_reg_data);
71 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
72 cs, mr_addr, mr);
73 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
74 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
75 ((mr
1119 u32 mr = 0, temp; local
[all...]
/u-boot/arch/sandbox/cpu/
H A Deth-raw-os.c73 struct packet_mreq mr; local
116 mr.mr_ifindex = device->sll_ifindex;
117 mr.mr_type = PACKET_MR_PROMISC;
119 &mr, sizeof(mr));
/u-boot/examples/api/
H A Dglue.c118 static struct mem_region mr[UB_MAX_MR]; variable in typeref:struct:mem_region
126 si.mr = mr;
128 memset(&mr, 0, sizeof(mr));
/u-boot/board/socionext/developerbox/
H A Ddeveloperbox.c128 struct mm_region *mr; local
148 mr = &mem_map[DDR_REGION_INDEX(0)];
149 mem_map[ri].attrs = mr->attrs;

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