1// SPDX-License-Identifier: GPL-2.0
2/*
3 * u-boot/board/socionext/developerbox/developerbox.c
4 *
5 * Copyright (C) 2016-2017 Socionext Inc.
6 * Copyright (C) 2021 Linaro Ltd.
7 */
8#include <asm/types.h>
9#include <asm/armv8/mmu.h>
10#include <asm/global_data.h>
11#include <asm/io.h>
12#include <common.h>
13#include <efi.h>
14#include <efi_loader.h>
15#include <env_internal.h>
16#include <fdt_support.h>
17#include <log.h>
18
19#include <linux/kernel.h>
20
21#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
22struct efi_fw_image fw_images[] = {
23	{
24		.image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID,
25		.fw_name = u"DEVELOPERBOX-FIP",
26		.image_index = 1,
27	},
28};
29
30struct efi_capsule_update_info update_info = {
31	.dfu_string = "mtd nor1=fip.bin raw 600000 400000",
32	.num_images = ARRAY_SIZE(fw_images),
33	.images = fw_images,
34};
35#endif /* EFI_HAVE_CAPSULE_SUPPORT */
36
37static struct mm_region sc2a11_mem_map[] = {
38	{
39		.virt = 0x0UL,
40		.phys = 0x0UL,
41		.size = 0x80000000UL,
42		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
43			 PTE_BLOCK_OUTER_SHARE
44	}, {
45		/* 1st DDR block */
46		.virt = 0x80000000UL,
47		.phys = 0x80000000UL,
48		.size = PHYS_SDRAM_SIZE,
49		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
50			 PTE_BLOCK_OUTER_SHARE
51	}, {
52		/* 2nd DDR place holder */
53		0,
54	}, {
55		/* 3rd DDR place holder */
56		0,
57	}, {
58		/* List terminator */
59		0,
60	}
61};
62
63struct mm_region *mem_map = sc2a11_mem_map;
64
65#define DDR_REGION_INDEX(i)	(1 + (i))
66#define MAX_DDR_REGIONS		3
67
68struct draminfo_entry {
69	u64	base;
70	u64	size;
71};
72
73struct draminfo {
74	u32	nr_regions;
75	u32	reserved;
76	struct draminfo_entry	entry[3];
77};
78
79DECLARE_GLOBAL_DATA_PTR;
80
81#define LOAD_OFFSET 0x100
82
83/* SCBM System MMU is used for eMMC and NETSEC */
84#define SCBM_SMMU_ADDR				(0x52e00000UL)
85#define SMMU_SCR0_OFFS				(0x0)
86#define SMMU_SCR0_SHCFG_INNER			(0x2 << 22)
87#define SMMU_SCR0_MTCFG				(0x1 << 20)
88#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB	(0xf << 16)
89
90static void synquacer_setup_scbm_smmu(void)
91{
92	writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB,
93	       SCBM_SMMU_ADDR + SMMU_SCR0_OFFS);
94}
95
96/*
97 * Miscellaneous platform dependent initialisations
98 */
99int board_init(void)
100{
101	gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
102
103	gd->env_addr = (ulong)&default_environment[0];
104
105	synquacer_setup_scbm_smmu();
106
107	return 0;
108}
109
110int ft_board_setup(void *blob, struct bd_info *bd)
111{
112	/* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
113	fdt_del_node_and_alias(blob, "spi_nor");
114	fdt_del_node_and_alias(blob, "i2c0");
115
116	return 0;
117}
118
119/*
120 * DRAM configuration
121 */
122
123int dram_init(void)
124{
125	struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
126	struct draminfo_entry *ent = synquacer_draminfo->entry;
127	unsigned long size = 0;
128	struct mm_region *mr;
129	int i, ri;
130
131	if (synquacer_draminfo->nr_regions < 1) {
132		log_err("Failed to get correct DRAM information\n");
133		return -EINVAL;
134	}
135
136	for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
137		if (i >= MAX_DDR_REGIONS)
138			break;
139
140		ri = DDR_REGION_INDEX(i);
141		mem_map[ri].phys = ent[i].base;
142		mem_map[ri].size = ent[i].size;
143		mem_map[ri].virt = mem_map[ri].phys;
144		size += ent[i].size;
145		if (i == 0)
146			continue;
147
148		mr = &mem_map[DDR_REGION_INDEX(0)];
149		mem_map[ri].attrs = mr->attrs;
150	}
151
152	gd->ram_size = size;
153	gd->ram_base = ent[0].base;
154
155	return 0;
156}
157
158phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
159{
160	struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
161	struct draminfo_entry *ent = synquacer_draminfo->entry;
162
163	return ent[synquacer_draminfo->nr_regions - 1].base +
164	       ent[synquacer_draminfo->nr_regions - 1].size;
165}
166
167int dram_init_banksize(void)
168{
169	struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
170	struct draminfo_entry *ent = synquacer_draminfo->entry;
171	int i;
172
173	for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
174		if (i < synquacer_draminfo->nr_regions) {
175			debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
176			gd->bd->bi_dram[i].start = ent[i].base;
177			gd->bd->bi_dram[i].size = ent[i].size;
178		}
179	}
180
181	return 0;
182}
183
184int print_cpuinfo(void)
185{
186	printf("CPU:   SC2A11:Cortex-A53 MPCore 24cores\n");
187	return 0;
188}
189