Searched refs:memc (Results 1 - 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mtmips/
H A Dddr_init.c68 static void mc_ddr_init(void __iomem *memc, const struct mc_ddr_cfg *cfg, argument
77 clrbits_32(memc + MEMCTL_SDRAM_CFG1_REG, RBC_MAPPING);
79 writel(cfg->cfg2, memc + MEMCTL_DDR_CFG2_REG);
80 writel(cfg->cfg3, memc + MEMCTL_DDR_CFG3_REG);
81 writel(cfg->cfg4, memc + MEMCTL_DDR_CFG4_REG);
82 writel(dq_dly, memc + MEMCTL_DDR_DQ_DLY_REG);
83 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG);
85 writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG);
93 writel(val, memc + MEMCTL_DDR_CFG1_REG);
95 clrsetbits_32(memc
203 mc_sdr_init(void __iomem *memc, mc_reset_t mc_reset, u32 cfg0, u32 cfg1) argument
[all...]
H A Dddr_cal.c35 static inline bool dqs_test_error(void __iomem *memc, u32 memsize, u32 dqsval, argument
46 writel(INIT_DQS_VAL, memc + MEMCTL_DDR_DQS_DLY_REG);
55 writel(dqsval, memc + MEMCTL_DDR_DQS_DLY_REG);
74 static inline int dqs_find_max(void __iomem *memc, u32 memsize, int initval, argument
82 if (dqs_test_error(memc, memsize, dqsval, 3))
89 static inline int dqs_find_min(void __iomem *memc, u32 memsize, int initval, argument
97 if (dqs_test_error(memc, memsize, dqsval, 1))
104 void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw) argument
115 clrbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN);
118 ddr_cfg2_reg = readl(memc
[all...]
/u-boot/arch/mips/mach-mtmips/include/mach/
H A Dddr.h36 void __iomem *memc; member in struct:mc_ddr_init_param
54 void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw);
/u-boot/drivers/clk/mtmips/
H A Dclk-mt7621.c191 static void mt7621_get_clocks(struct mt7621_clk_priv *priv, struct regmap *memc) argument
215 regmap_read(memc, MEMPLL18_REG, &mempll);
229 regmap_read(memc, MEMPLL6_REG, &mempll);
235 regmap_read(memc, MEMPLL1_REG, &bs);
250 struct regmap *memc; local
261 /* get corresponding memc phandle */
262 ret = dev_read_phandle_with_args(dev, "mediatek,memc", NULL, 0, 0,
267 memc = syscon_node_to_regmap(args.node);
268 if (IS_ERR(memc))
269 return PTR_ERR(memc);
[all...]
/u-boot/arch/mips/mach-mtmips/mt7628/
H A Dddr.c150 param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE);
171 ddr_calibrate(param.memc, param.memsize, param.bus_width);
/u-boot/arch/mips/mach-mtmips/mt7620/
H A Ddram.c86 param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE);

Completed in 106 milliseconds