1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8#include <asm/addrspace.h> 9#include <asm/global_data.h> 10#include <linux/bitops.h> 11#include <linux/delay.h> 12#include <linux/sizes.h> 13#include <linux/io.h> 14#include <mach/ddr.h> 15#include <mach/mc.h> 16#include "mt7628.h" 17 18DECLARE_GLOBAL_DATA_PTR; 19 20/* DDR2 DQ_DLY */ 21#define DDR2_DQ_DLY \ 22 ((0x8 << DQ1_DELAY_COARSE_TUNING_S) | \ 23 (0x2 << DQ1_DELAY_FINE_TUNING_S) | \ 24 (0x8 << DQ0_DELAY_COARSE_TUNING_S) | \ 25 (0x2 << DQ0_DELAY_FINE_TUNING_S)) 26 27/* DDR2 DQS_DLY */ 28#define DDR2_DQS_DLY \ 29 ((0x8 << DQS1_DELAY_COARSE_TUNING_S) | \ 30 (0x3 << DQS1_DELAY_FINE_TUNING_S) | \ 31 (0x8 << DQS0_DELAY_COARSE_TUNING_S) | \ 32 (0x3 << DQS0_DELAY_FINE_TUNING_S)) 33 34const struct mc_ddr_cfg ddr1_cfgs_200mhz[] = { 35 [DRAM_8MB] = { 0x34A1EB94, 0x20262324, 0x28000033, 0x00000002, 0x00000000 }, 36 [DRAM_16MB] = { 0x34A1EB94, 0x202A2324, 0x28000033, 0x00000002, 0x00000000 }, 37 [DRAM_32MB] = { 0x34A1E5CA, 0x202E2324, 0x28000033, 0x00000002, 0x00000000 }, 38 [DRAM_64MB] = { 0x3421E5CA, 0x20322324, 0x28000033, 0x00000002, 0x00000000 }, 39 [DRAM_128MB] = { 0x241B05CA, 0x20362334, 0x28000033, 0x00000002, 0x00000000 }, 40}; 41 42const struct mc_ddr_cfg ddr1_cfgs_160mhz[] = { 43 [DRAM_8MB] = { 0x239964A1, 0x20262323, 0x00000033, 0x00000002, 0x00000000 }, 44 [DRAM_16MB] = { 0x239964A1, 0x202A2323, 0x00000033, 0x00000002, 0x00000000 }, 45 [DRAM_32MB] = { 0x239964A1, 0x202E2323, 0x00000033, 0x00000002, 0x00000000 }, 46 [DRAM_64MB] = { 0x239984A1, 0x20322323, 0x00000033, 0x00000002, 0x00000000 }, 47 [DRAM_128MB] = { 0x239AB4A1, 0x20362333, 0x00000033, 0x00000002, 0x00000000 }, 48}; 49 50const struct mc_ddr_cfg ddr2_cfgs_200mhz[] = { 51 [DRAM_32MB] = { 0x2519E2E5, 0x222E2323, 0x68000C43, 0x00000452, 0x0000000A }, 52 [DRAM_64MB] = { 0x249AA2E5, 0x22322323, 0x68000C43, 0x00000452, 0x0000000A }, 53 [DRAM_128MB] = { 0x249B42E5, 0x22362323, 0x68000C43, 0x00000452, 0x0000000A }, 54 [DRAM_256MB] = { 0x249CE2E5, 0x223A2323, 0x68000C43, 0x00000452, 0x0000000A }, 55}; 56 57const struct mc_ddr_cfg ddr2_cfgs_160mhz[] = { 58 [DRAM_32MB] = { 0x23918250, 0x222E2322, 0x40000A43, 0x00000452, 0x00000006 }, 59 [DRAM_64MB] = { 0x239A2250, 0x22322322, 0x40000A43, 0x00000452, 0x00000008 }, 60 [DRAM_128MB] = { 0x2392A250, 0x22362322, 0x40000A43, 0x00000452, 0x00000008 }, 61 [DRAM_256MB] = { 0x24140250, 0x223A2322, 0x40000A43, 0x00000452, 0x00000008 }, 62}; 63 64static void mt7628_memc_reset(int assert) 65{ 66 void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); 67 68 if (assert) 69 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); 70 else 71 clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); 72} 73 74static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type) 75{ 76 void __iomem *rgc = ioremap_nocache(RGCTL_BASE, RGCTL_SIZE); 77 u32 ck_pad1, cmd_pad1, dq_pad0, dq_pad1, dqs_pad0, dqs_pad1; 78 79 setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); 80 81 if (ddr_type == DRAM_DDR1) 82 setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); 83 else 84 clrbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); 85 86 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); 87 88 __udelay(250 * 50); 89 90 setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); 91 setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); 92 93 ck_pad1 = readl(rgc + RGCTL_DDR_PAD_CK_G1_REG); 94 cmd_pad1 = readl(rgc + RGCTL_DDR_PAD_CMD_G1_REG); 95 dq_pad0 = readl(rgc + RGCTL_DDR_PAD_DQ_G0_REG); 96 dq_pad1 = readl(rgc + RGCTL_DDR_PAD_DQ_G1_REG); 97 dqs_pad0 = readl(rgc + RGCTL_DDR_PAD_DQS_G0_REG); 98 dqs_pad1 = readl(rgc + RGCTL_DDR_PAD_DQS_G1_REG); 99 100 ck_pad1 &= ~(DRVP_M | DRVN_M); 101 cmd_pad1 &= ~(DRVP_M | DRVN_M); 102 dq_pad0 &= ~RTT_M; 103 dq_pad1 &= ~(DRVP_M | DRVN_M); 104 dqs_pad0 &= ~RTT_M; 105 dqs_pad1 &= ~(DRVP_M | DRVN_M); 106 107 if (pkg_type == PKG_ID_KN) { 108 ck_pad1 |= (3 << DRVP_S) | (3 << DRVN_S); 109 cmd_pad1 |= (3 << DRVP_S) | (3 << DRVN_S); 110 dq_pad1 |= (3 << DRVP_S) | (3 << DRVN_S); 111 dqs_pad1 |= (3 << DRVP_S) | (3 << DRVN_S); 112 } else { 113 ck_pad1 |= (12 << DRVP_S) | (12 << DRVN_S); 114 cmd_pad1 |= (2 << DRVP_S) | (2 << DRVN_S); 115 dqs_pad1 |= (12 << DRVP_S) | (12 << DRVN_S); 116 if (ddr_type == DRAM_DDR1) 117 dq_pad1 |= (7 << DRVP_S) | (7 << DRVN_S); 118 else 119 dq_pad1 |= (4 << DRVP_S) | (4 << DRVN_S); 120 } 121 122 writel(ck_pad1, rgc + RGCTL_DDR_PAD_CK_G1_REG); 123 writel(cmd_pad1, rgc + RGCTL_DDR_PAD_CMD_G1_REG); 124 writel(dq_pad0, rgc + RGCTL_DDR_PAD_DQ_G0_REG); 125 writel(dq_pad1, rgc + RGCTL_DDR_PAD_DQ_G1_REG); 126 writel(dqs_pad0, rgc + RGCTL_DDR_PAD_DQS_G0_REG); 127 writel(dqs_pad1, rgc + RGCTL_DDR_PAD_DQS_G1_REG); 128} 129 130void mt7628_ddr_init(void) 131{ 132 void __iomem *sysc; 133 int ddr_type, pkg_type, lspd; 134 struct mc_ddr_init_param param; 135 136 sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); 137 ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE; 138 pkg_type = !!(readl(sysc + SYSCTL_CHIP_REV_ID_REG) & PKG_ID); 139 lspd = readl(sysc + SYSCTL_CLKCFG0_REG) & 140 (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL); 141 142 if (pkg_type == PKG_ID_KN) 143 ddr_type = DRAM_DDR1; 144 145 mt7628_memc_reset(1); 146 __udelay(200); 147 148 mt7628_ddr_pad_ldo_config(ddr_type, pkg_type); 149 150 param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE); 151 param.dq_dly = DDR2_DQ_DLY; 152 param.dqs_dly = DDR2_DQS_DLY; 153 param.mc_reset = mt7628_memc_reset; 154 param.memsize = 0; 155 param.bus_width = 0; 156 157 if (ddr_type == DRAM_DDR1) { 158 if (lspd) 159 param.cfgs = ddr1_cfgs_160mhz; 160 else 161 param.cfgs = ddr1_cfgs_200mhz; 162 ddr1_init(¶m); 163 } else { 164 if (lspd) 165 param.cfgs = ddr2_cfgs_160mhz; 166 else 167 param.cfgs = ddr2_cfgs_200mhz; 168 ddr2_init(¶m); 169 } 170 171 ddr_calibrate(param.memc, param.memsize, param.bus_width); 172 173 gd->ram_size = param.memsize; 174} 175