Searched refs:link_rate (Results 1 - 8 of 8) sorted by relevance

/u-boot/drivers/video/
H A Dlogicore_dp_tx.c153 * @link_rate: Currently selected link rate for this link
167 u8 link_rate; member in struct:link_config
694 * @link_rate: The link rate to be checked for validity
698 static bool is_link_rate_valid(struct udevice *dev, u8 link_rate) argument
703 if (link_rate != LINK_BW_SET_162GBPS &&
704 link_rate != LINK_BW_SET_270GBPS &&
705 link_rate != LINK_BW_SET_540GBPS)
707 else if (link_rate > dp_tx->link_config.max_link_rate)
961 * @link_rate: The link rate to set (one of LINK_BW_SET_*)
968 static int set_link_rate(struct udevice *dev, u8 link_rate) argument
[all...]
/u-boot/drivers/video/rockchip/
H A Drk_edp.c353 values[0] = edp->link_train.link_rate;
631 edp->link_train.link_rate = values[1];
635 edp->link_train.link_rate * 27 / 100,
636 edp->link_train.link_rate * 27 % 100,
639 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
640 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
642 edp->link_train.link_rate);
666 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
/u-boot/drivers/video/zynqmp/
H A Dzynqmp_dpsub.c883 * @link_rate: The link rate to set (one of LINK_BW_SET_*)
890 static int set_link_rate(struct udevice *dev, u8 link_rate) argument
896 switch (link_rate) {
913 dp_sub->link_config.link_rate = link_rate;
915 writel(dp_sub->link_config.link_rate,
921 &dp_sub->link_config.link_rate);
1568 link_config->max_link_rate : dp_sub->link_rate);
1581 debug("Link rate =%d\n", dp_sub->link_config.link_rate);
1628 msa_config->n_vid = 27 * 1000 * link_config->link_rate;
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H A Dzynqmp_dpsub.h109 * @link_rate: Currently selected link rate for this link
124 u8 link_rate; member in struct:link_config
292 u8 link_rate; member in struct:zynqmp_dpsub_priv
/u-boot/drivers/video/tegra124/
H A Ddp.c487 const u32 link_rate = 27 * link_cfg->link_bw * 1000 * 1000; local
509 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ ||
514 (u64)link_rate * 8 * link_cfg->lane_count)
517 num_linkclk_line = (u32)(lldiv(link_rate * timing->hactive.typ,
522 do_div(ratio_f, link_rate * link_cfg->lane_count);
623 link_rate, timing->pixelclock.typ) -
639 * link_rate, timing->pixelclock.typ) - (36 /
/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dedp_rk3288.h634 u8 link_rate; member in struct:link_train
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-pcieepx-defs.h5879 u32 link_rate : 4; member in struct:cvmx_pcieepx_cfg452::cvmx_pcieepx_cfg452_s
5929 u32 link_rate : 4; member in struct:cvmx_pcieepx_cfg452::cvmx_pcieepx_cfg452_cn70xx
H A Dcvmx-pciercx-defs.h4617 u32 link_rate : 4; member in struct:cvmx_pciercx_cfg452::cvmx_pciercx_cfg452_s
4667 u32 link_rate : 4; member in struct:cvmx_pciercx_cfg452::cvmx_pciercx_cfg452_cn70xx

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