Searched refs:im (Results 1 - 15 of 15) sorted by relevance

/u-boot/board/gdsys/mpc8308/
H A Dsdram.c36 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
40 out_be32(&im->sysconf.ddrlaw[0].bar,
42 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
43 out_be32(&im->sysconf.ddrcdr, CFG_SYS_DDRCDR_VALUE);
45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
46 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
49 out_be32(&im->ddr.cs_config[1], 0);
51 out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL);
52 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
53 out_be32(&im
74 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
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/u-boot/board/cssi/cmpcpro/
H A Dcmpcpro.c121 immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; local
124 out_be32(&im->qepio.ioport[0].pdat, 0x00808000);
125 out_be32(&im->qepio.ioport[0].podr, 0x00008000);
126 out_be32(&im->qepio.ioport[0].dir1, 0x40800968);
127 out_be32(&im->qepio.ioport[0].dir2, 0x650A0896);
128 out_be32(&im->qepio.ioport[0].ppar1, 0x40400204);
129 out_be32(&im->qepio.ioport[0].ppar2, 0x05050464);
132 out_be32(&im->qepio.ioport[1].pdat, 0x00018000);
133 out_be32(&im->qepio.ioport[1].podr, 0x00000000);
134 out_be32(&im
158 immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; local
195 immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; local
232 immap_t __iomem *im = (immap_t *)CONFIG_SYS_IMMR; local
299 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; local
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/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspl_minimal.c26 void cpu_init_f (volatile immap_t * im) argument
37 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
43 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
49 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
54 im->sysconf.spcr |= SPCR_TBEN;
58 im->sysconf.ddrcdr = CFG_SYS_DDRCDR;
62 im
103 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
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H A Dcpu_init.c63 void cpu_init_f (volatile immap_t * im) argument
148 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
150 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
152 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
155 gd->arch.reset_status = __raw_readl(&im->reset.rsr);
156 __raw_writel(~(RSR_RES), &im->reset.rsr);
159 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
160 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
166 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
171 clrsetbits_be32(&im
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H A Dspeed.c81 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
130 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
133 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
135 if (im->reset.rcwh & HRCWH_PCI_HOST) {
149 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
152 sccr = im->clk.sccr;
366 (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
367 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
380 (1 + ((im
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H A Dqe_io.c99 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
100 qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
H A Dpcie.c40 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
48 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
49 sccr = im->clk.sccr;
51 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
/u-boot/include/
H A Dioports.h21 * memory map (im) of the set of registers for a port (idx)
27 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
29 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
/u-boot/board/freescale/mpc837xerdb/
H A Dmpc837xerdb.c71 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
74 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
99 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; local
103 im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
104 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
106 im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
109 im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
112 im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS;
113 im
182 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; local
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/u-boot/board/keymile/km83xx/
H A Dkm83xx.c210 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
215 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
216 out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f);
217 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
218 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
219 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
220 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
221 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
222 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
223 out_be32(&im
252 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
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/u-boot/drivers/clk/
H A Dmpc83xx_clk.h272 * @im: Pointer to the MPC83xx main register map in question
276 static inline u32 get_spmr(immap_t *im) argument
278 u32 res = in_be32(&im->clk.spmr);
285 * @im: Pointer to the MPC83xx main register map in question
289 static inline u32 get_sccr(immap_t *im) argument
291 u32 res = in_be32(&im->clk.sccr);
298 * @im: Pointer to the MPC83xx main register map in question
302 static inline u32 get_lcrr(immap_t *im) argument
304 u32 res = in_be32(&im->im_lbc.lcrr);
311 * @im
315 get_pci_sync_in(immap_t *im) argument
329 get_csb_clk(immap_t *im) argument
344 spmr_field(immap_t *im, u32 mask) argument
359 sccr_field(immap_t *im, u32 mask) argument
374 lcrr_field(immap_t *im, u32 mask) argument
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H A Dmpc83xx_clk.c108 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
112 u32 csb_clk = get_csb_clk(im);
130 switch (sccr_field(im, mask)) {
153 priv->speed[clk] = csb_clk * (1 + sccr_field(im, mask));
163 u32 pci_sync_in = get_pci_sync_in(im);
164 u32 qepmf = spmr_field(im, SPMR_CEPMF);
165 u32 qepdf = spmr_field(im, SPMR_CEPDF);
178 (1 + spmr_field(im, SPMR_LBIUCM));
179 u32 clkdiv = lcrr_field(im, LCRR_CLKDIV);
199 u8 corepll = spmr_field(im, SPMR_COREPL
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/u-boot/drivers/serial/
H A Dserial_mpc8xx.c65 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; local
66 cpm8xx_t __iomem *cp = &(im->im_cpm);
83 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; local
87 cpm8xx_t __iomem *cp = &(im->im_cpm);
103 out_be32(&im->im_siu_conf.sc_sdcr, 1);
106 out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
109 out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
175 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; local
176 cpm8xx_t __iomem *cpmp = &(im->im_cpm);
193 immap_t __iomem *im local
222 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; local
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/u-boot/drivers/ram/
H A Dmpc83xx_sdram.c144 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
152 out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000);
153 out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1));
155 out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24);
282 out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge |
312 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
361 out_be32(&im->ddr.cs_config[0], 0);
362 out_be32(&im->ddr.cs_config[1], 0);
438 out_be32(&im->sysconf.ddrcdr, ddrcdr);
489 out_be32(&im
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/u-boot/drivers/pinctrl/
H A Dpinctrl-qe-io.c117 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; local
118 qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;

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