/u-boot/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_hw_algo.c | 43 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) argument 55 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 58 CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id, 61 val = data_read[if_id]; 77 (dev_num, if_id, 101 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 105 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 113 int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4]) argument 126 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, 162 u32 pup = 0, if_id local 631 u32 if_id = 0; local [all...] |
H A D | ddr3_training_pbs.c | 48 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; local 58 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { 59 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 63 (dev_num, ACCESS_TYPE_UNICAST, if_id, 68 (dev_num, ACCESS_TYPE_UNICAST, if_id, 88 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id 942 u32 data_value = 0, bit = 0, if_id = 0, pup = 0; local 992 u32 if_id, pup, bit; local [all...] |
H A D | ddr3_training_centralization.c | 60 u32 if_id, pattern_id, bit_id; local 85 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { 86 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 89 (dev_num, ACCESS_TYPE_UNICAST, if_id, 93 (dev_num, ACCESS_TYPE_UNICAST, if_id, 108 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id 529 u32 if_id, pup_id, pattern_id, bit_id; local 730 u32 if_id = 0, bus_id = 0; local [all...] |
H A D | ddr3_training_leveling.c | 25 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id, 27 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id, 41 u32 bus_num, if_id, cl_val; local 55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) 56 rl_values[effective_cs][bus_num][if_id] = 0; 59 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id 317 u32 c_cs, if_id, cs_mask = 0; local 358 u32 c_cs, if_id, cs_mask = 0; local 400 u32 bus_num, if_id, cl_val, bit_num; local 764 ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs, u32 *cs_mask) argument 807 u32 reg_data = 0, temp = 0, iter, if_id, bus_cnt; local 1175 u32 if_id, bus_id, data, data_tmp; local 1285 ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id, u32 bus_id) argument 1365 ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id, u32 edge_offset) argument 1604 u32 bus_id = 0, if_id = 0; local 1724 mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq) argument [all...] |
H A D | ddr3_debug.c | 135 u32 if_id, reg_addr, data_value, bus_id; local 143 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { 144 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 147 if_id, reg_addr, read_data, 149 printf("0x%x ", read_data[if_id]); 157 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id 371 u32 if_id = 0; local 578 u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0; local 796 u32 if_id = 0, bus_id = 0; local 829 u32 if_id = 0, bus_id = 0; local 865 u32 if_id = 0, bus_id = 0; local 892 u32 if_id = 0, bus_id = 0; local 954 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0; local 1024 ddr3_tip_compare(u32 if_id, u32 *p_src, u32 *p_dst, u32 byte_index) argument 1069 int if_id = 0; local 1216 int if_id = 0, gap = 0; local 1462 u32 seq = 0, if_id = 0, addr, cnt; local [all...] |
H A D | ddr3_training.c | 102 u32 if_id, u32 cl_value, u32 cwl_value); 110 u32 if_id, enum mv_ddr_freq frequency); 112 u32 if_id, enum mv_ddr_freq frequency); 115 u32 if_id, enum mv_ddr_freq frequency); 249 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id); 300 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) argument 313 data = (tm->interface_params[if_id].bus_width == 316 (dev_num, ACCESS_TYPE_UNICAST, if_id, 319 mem_index = tm->interface_params[if_id].memory_size; 323 (dev_num, ACCESS_TYPE_UNICAST, if_id, 364 u32 if_id; local 708 ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id) argument 762 ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id) argument 795 ddr3_tip_rank_control(u32 dev_num, u32 if_id) argument 1023 ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, u32 if_id, u32 reg_addr, u32 data_value, u32 mask) argument 1034 ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, u32 if_id, u32 reg_addr, u32 *data, u32 mask) argument 1045 ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, u32 if_id, u32 exp_value, u32 mask, u32 offset, u32 poll_tries) argument 1097 ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access, u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data) argument 1108 ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access, u32 if_id, enum hws_access_type phy_access, u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 data_value) argument 1126 u32 data_val = 0, if_id, start_if, end_if; local 1155 adll_calibration(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument 1228 ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument 1646 ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, u32 if_id, u32 cl_value, u32 cwl_value) argument 1679 ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument 1829 ddr4_tip_set_timing(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument 1891 u32 if_id, bus_num, cs_bitmask, data_val, cs_num; local 1931 u32 if_id; local 1962 u32 if_id = 0; local 2001 u32 if_id, phy_id, cs; local 2103 u32 if_id, phy_id; local 2134 u32 if_id; local 2605 u32 if_id, stage; local 2674 u32 if_id = 0, mem_mask = 0, bus_index = 0; local 2792 hws_ddr3_get_device_width(u32 if_id) argument 2800 hws_ddr3_get_device_size(u32 if_id) argument 2815 hws_ddr3_calc_mem_cs_size(u32 if_id, u32 cs, u32 *cs_size) argument 2847 hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr) argument [all...] |
H A D | mv_ddr4_training_calibration.c | 69 static int mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 mode, u8 *vw_l, u8 *vw_h, u8 *vw_v, 76 u32 if_id, subphy_num; local 106 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { 108 valid_vref_cnt[if_id][subphy_num] = 0; 109 vref_state_per_subphy[if_id][subphy_num] = MV_DDR4_VREF_SUBPHY_CAL_ABOVE; 151 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id 342 u32 if_id, subphy_num, pattern_id, pattern_loop_idx, bit_num; local 945 mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 mode, u8 *vw_l, u8 *vw_h, u8 *vw_v, u8 vw_num, u8 *v_opt, u8 *t_opt) argument 1630 u32 if_id, subphy_num; local [all...] |
H A D | ddr3_training_hw_algo.h | 10 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
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H A D | ddr3_training_leveling.h | 12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
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H A D | mv_ddr4_mpr_pda_if.c | 42 u32 if_id; local 61 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { 62 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 63 cl = tm->interface_params[if_id].cas_l; 64 cwl = tm->interface_params[if_id].cas_wl; 65 t_ckclk = MEGA / mv_ddr_freq_get(tm->interface_params[if_id].memory_freq); 66 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get(tm->interface_params[if_id].speed_bin_index, 88 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR0_RE 192 u32 val, mask, if_id = 0; local 226 u32 val, mask, if_id = 0; local 292 u32 word_idx, if_id = 0; local 333 u32 if_id = 0, val = 0, mask; local 434 mv_ddr4_vref_training_mode_ctrl(u8 dev_num, u8 if_id, enum hws_access_type access_type, int enable) argument 475 mv_ddr4_vref_tap_set(u8 dev_num, u8 if_id, enum hws_access_type access_type, u32 taps_num, enum mv_ddr4_vref_tap_state state) argument 523 mv_ddr4_vref_set(u8 dev_num, u8 if_id, enum hws_access_type access_type, u32 range, u32 vdq_tv, u8 vdq_training_ena) argument 572 mv_ddr4_pda_pattern_odpg_load(u32 dev_num, enum hws_access_type access_type, u32 if_id, u32 subphy_mask, u32 cs_num) argument 629 mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable) argument [all...] |
H A D | mv_ddr4_training.c | 43 u32 if_id; local 47 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { 48 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 51 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, SDRAM_CFG_REG, 57 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_PINS_MUX_REG, 66 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_DLL_TIMING_REG, 72 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_ZQ_INIT_TIMIMG_REG, 78 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_ZQ_TIMING_RE 295 u8 i, if_id = 0; local 470 u32 if_id; local [all...] |
H A D | ddr3_training_ip_flow.h | 67 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, 70 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id, 74 u32 if_id, u32 reg_addr, u32 data_value, u32 mask); 76 u32 if_id, u32 exp_value, u32 mask, u32 offset, 79 u32 if_id, u32 reg_addr, u32 *data, u32 mask); 82 u32 if_id, u32 phy_id, 85 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access, 89 u32 if_id, enum hws_access_type e_phy_access, u32 phy_id, 92 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id, 96 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u3 [all...] |
H A D | mv_ddr4_mpr_pda_if.h | 46 int mv_ddr4_vref_training_mode_ctrl(u8 dev_num, u8 if_id, 49 int mv_ddr4_vref_tap_set(u8 dev_num, u8 if_id, 53 int mv_ddr4_vref_set(u8 dev_num, u8 if_id, enum hws_access_type access_type, 56 u32 if_id, u32 subphy_mask, u32 cs_num); 57 int mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable);
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H A D | ddr3_training_ip_engine.c | 503 ("if_id %d not valid\n", 713 u32 if_id, enum hws_pattern pattern, 725 (dev_num, access_type, if_id, 731 (dev_num, access_type, if_id, 738 (dev_num, access_type, if_id, 744 (dev_num, access_type, if_id, 751 (dev_num, access_type, if_id, 757 (dev_num, access_type, if_id, 767 u32 if_id, enum hws_dir direction, u32 tx_phases, 779 ret = ddr3_tip_if_write(dev_num, access_type, if_id, 712 ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum hws_pattern pattern, u32 load_addr) argument 766 ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum hws_dir direction, u32 tx_phases, u32 tx_burst_size, u32 rx_phases, u32 delay_between_burst, u32 rd_mode, u32 cs_num, u32 addr_stress_jump, u32 single_pattern) argument 833 ddr3_tip_read_training_result(u32 dev_num, u32 if_id, enum hws_access_type pup_access_type, u32 pup_num, u32 bit_num, enum hws_search_dir search, enum hws_dir direction, enum hws_training_result result_type, enum hws_training_load_op operation, u32 cs_num_type, u32 **load_res, int is_read_from_db, u8 cons_tap, int is_check_result_validity) argument 994 u32 pattern = 0, if_id; local 1024 u32 reg_data, if_id; local 1103 ddr3_tip_ip_training_wrapper_int(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum hws_access_type pup_access_type, u32 pup_num, u32 bit_num, enum hws_training_result result_type, enum hws_control_element control_element, enum hws_search_dir search_dir, enum hws_dir direction, u32 interface_mask, u32 init_value_l2h, u32 init_value_h2l, u32 num_iter, enum hws_pattern pattern, enum hws_edge_compare edge_comp, enum hws_ddr_cs train_cs_type, u32 cs_num, enum hws_training_ip_stat *train_status) argument 1242 ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum hws_access_type pup_access_type, u32 pup_num, enum hws_training_result result_type, enum hws_control_element control_element, enum hws_search_dir search_dir, enum hws_dir direction, u32 interface_mask, u32 init_value_l2h, u32 init_value_h2l, u32 num_iter, enum hws_pattern pattern, enum hws_edge_compare edge_comp, enum hws_ddr_cs train_cs_type, u32 cs_num, enum hws_training_ip_stat *train_status) argument 1593 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id) argument 1598 mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data) argument 1608 u32 bus_cnt = 0, if_id, dev_num = 0; local 1675 u32 pattern, if_id, pup_id; local [all...] |
H A D | ddr3_training_ip_prv_if.h | 25 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 28 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 38 u8 dev_num, u32 if_id, enum mv_ddr_freq freq); 47 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id, 51 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type, 56 u32 dev_num, enum hws_access_type access_type, u32 if_id, 68 enum hws_static_config_type static_config_type, u32 if_id); 70 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data); 72 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data); 81 u32 dev_num, u32 if_id, struc [all...] |
H A D | mv_ddr4_training_leveling.c | 18 static u8 mv_ddr4_xsb_comp_test(u32 dev_num, u32 subphy_num, u32 if_id, argument 169 status = ddr3_tip_ext_read(dev_num, if_id, pattern_table[PATTERN_TEST].start_addr << 3, 179 status = ddr3_tip_ext_read(dev_num, if_id, ((pattern_table[PATTERN_TEST].start_addr << 3) + 191 status = ddr3_tip_bus_read(dev_num, if_id, ACCESS_TYPE_UNICAST, subphy_num, DDR_PHY_DATA, 274 u32 if_id; local 339 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { 340 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); 345 status = ddr3_tip_bus_read(dev_num, if_id, ACCESS_TYPE_UNICAS [all...] |
H A D | ddr3_training_ip_engine.h | 42 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id, 64 u32 if_id, 77 u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id); 78 void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data);
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H A D | mv_ddr_plat.c | 264 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, 851 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, argument 860 if (if_id != 0) { 863 if_id)); 974 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, argument 988 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, argument 1492 u32 if_id, phy_id; local 1530 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id 1575 u8 if_id = 0; local [all...] |
H A D | ddr3_training_bist.c | 14 u32 if_id, 74 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, argument 81 if (IS_IF_ACTIVE(tm->if_act_mask, if_id) == 0) 84 ("ddr3_tip_bist_read_result if_id %d\n", 85 if_id)); 86 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 91 pst_bist_result->bist_fail_high = read_data[if_id]; 92 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 97 pst_bist_result->bist_fail_low = read_data[if_id]; 99 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 167 ddr3_tip_bist_operation(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum hws_bist_operation oper_type) argument [all...] |
H A D | ddr3_training_ip_bist.h | 35 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
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H A D | mv_ddr_topology.h | 341 #define IS_IF_ACTIVE(if_mask, if_id) \ 342 ((if_mask) & (1 << (if_id))) 350 #define IS_BUS_ACTIVE(if_mask , if_id) \ 351 (((if_mask) >> (if_id)) & 1)
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H A D | ddr3_init.h | 187 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
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/u-boot/drivers/net/fsl-mc/ |
H A D | dprc.c | 208 cmd_params->ep1_interface_id = cpu_to_le16(endpoint1->if_id); 210 cmd_params->ep2_interface_id = cpu_to_le16(endpoint2->if_id); 244 cmd_params->interface_id = cpu_to_le32(endpoint->if_id); 282 cmd_params->ep1_interface_id = cpu_to_le16(endpoint1->if_id); 294 endpoint2->if_id = le16_to_cpu(rsp_params->ep2_interface_id);
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/u-boot/include/fsl-mc/ |
H A D | fsl_dprc.h | 198 * @if_id: Interface ID; should be set for endpoints with multiple 204 u16 if_id; member in struct:dprc_endpoint
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/u-boot/include/linux/usb/ |
H A D | composite.h | 74 * @if_id: Interface id 82 int if_id; member in struct:usb_os_desc_table
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